Move firewall related code to new firewall.c, to share
code in Stratix 10 and Agilex.
No functional change.
Signed-off-by: Ley Foon Tan <ley.foon....@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschm...@gmail.com>
---
v3:
- Move SOCFPGA_FIREWALL_TCU to firewall.c
---
arch/arm/mach-socfpga/Makefile | 1 +
.../mach-socfpga/{spl_s10.c => firewall.c} | 112 ++----------------
.../mach/{firewall_s10.h => firewall.h} | 10 +-
arch/arm/mach-socfpga/spl_s10.c | 87 +-------------
drivers/ddr/altera/sdram_s10.c | 2 +-
5 files changed, 21 insertions(+), 191 deletions(-)
copy arch/arm/mach-socfpga/{spl_s10.c => firewall.c} (51%)
rename arch/arm/mach-socfpga/include/mach/{firewall_s10.h => firewall.h} (94%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index fc1181cb27..dab34d0ef2 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -51,6 +51,7 @@ ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
obj-y += spl_a10.o
endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y += firewall.o
obj-y += spl_s10.o
endif
endif
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/firewall.c
similarity index 51%
copy from arch/arm/mach-socfpga/spl_s10.c
copy to arch/arm/mach-socfpga/firewall.c
index 8669ce0999..ab2cf1df1f 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/firewall.c
@@ -1,44 +1,14 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
*
*/
#include <asm/io.h>
-#include <asm/u-boot.h>
-#include <asm/utils.h>
#include <common.h>
-#include <debug_uart.h>
-#include <image.h>
-#include <spl.h>
-#include <asm/arch/clock_manager.h>
-#include <asm/arch/firewall_s10.h>
-#include <asm/arch/mailbox_s10.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/arch/system_manager.h>
-#include <watchdog.h>
-#include <dm/uclass.h>
+#include <asm/arch/firewall.h>
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 spl_boot_device(void)
-{
- /* TODO: Get from SDM or handoff */
- return BOOT_DEVICE_MMC1;
-}
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(const u32 boot_device)
-{
-#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
- return MMCSD_MODE_FS;
-#else
- return MMCSD_MODE_RAW;
-#endif
-}
-#endif
-
-void spl_disable_firewall_l4_per(void)
+static void firewall_l4_per_disable(void)
{
const struct socfpga_firwall_l4_per *firwall_l4_per_base =
(struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
@@ -78,7 +48,7 @@ void spl_disable_firewall_l4_per(void)
writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
}
-void spl_disable_firewall_l4_sys(void)
+static void firewall_l4_sys_disable(void)
{
const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
(struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
@@ -112,79 +82,19 @@ void spl_disable_firewall_l4_sys(void)
writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
}
-void board_init_f(ulong dummy)
+static void firewall_bridge_disable(void)
{
- const struct cm_config *cm_default_cfg = cm_get_default_config();
- int ret;
-
-#ifdef CONFIG_HW_WATCHDOG
- /* Ensure watchdog is paused when debugging is happening */
- SYSMGR_WRITEL(SYSMGR_WDDBG_PAUSE_ALL_CPU, SYSMGR_WDDBG);
-
- /* Enable watchdog before initializing the HW */
- socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
- socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
- hw_watchdog_init();
-#endif
-
- /* ensure all processors are not released prior Linux boot */
- writeq(0, CPU_RELEASE_ADDR);
-
- socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
- timer_init();
-
- sysmgr_pinmux_init();
-
- /* configuring the HPS clocks */
- cm_basic_init(cm_default_cfg);
-
-#ifdef CONFIG_DEBUG_UART
- socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
- debug_uart_init();
-#endif
- ret = spl_early_init();
- if (ret) {
- debug("spl_early_init() failed: %d\n", ret);
- hang();
- }
-
- preloader_console_init();
- cm_print_clock_quick_summary();
-
- /* enable non-secure interface to DMA330 DMA and peripherals */
- SYSMGR_WRITEL(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, SYSMGR_DMA);
- SYSMGR_WRITEL(SYSMGR_DMAPERIPH_ALL_NS, SYSMGR_DMA_PERIPH);
-
- spl_disable_firewall_l4_per();
-
- spl_disable_firewall_l4_sys();
-
/* disable lwsocf2fpga and soc2fpga bridge security */
writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
/* disable SMMU security */
writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
+}
- /* disable ocram security at CCU for non secure access */
- clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
- CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
- clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
- CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
-
-#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
- struct udevice *dev;
-
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- hang();
- }
-#endif
-
- mbox_init();
-
-#ifdef CONFIG_CADENCE_QSPI
- mbox_qspi_open();
-#endif
+void firewall_setup(void)
+{
+ firewall_l4_per_disable();
+ firewall_l4_sys_disable();
+ firewall_bridge_disable();
}
diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h
b/arch/arm/mach-socfpga/include/mach/firewall.h
similarity index 94%
rename from arch/arm/mach-socfpga/include/mach/firewall_s10.h
rename to arch/arm/mach-socfpga/include/mach/firewall.h
index b96f779f14..516bd1c0e1 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -1,11 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0
*
- * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
*
*/
-#ifndef _FIREWALL_S10_
-#define _FIREWALL_S10_
+#ifndef _FIREWALL_H_
+#define _FIREWALL_H_
struct socfpga_firwall_l4_per {
u32 nand; /* 0x00 */
@@ -117,4 +117,6 @@ struct socfpga_firwall_l4_sys {
#define FW_MPU_DDR_SCR_WRITEL(data, reg) \
writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg))
-#endif /* _FIREWALL_S10_ */
+void firewall_setup(void);
+
+#endif /* _FIREWALL_H_ */
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index 8669ce0999..5a0ce49e84 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -12,7 +12,7 @@
#include <image.h>
#include <spl.h>
#include <asm/arch/clock_manager.h>
-#include <asm/arch/firewall_s10.h>
+#include <asm/arch/firewall.h>
#include <asm/arch/mailbox_s10.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
@@ -38,80 +38,6 @@ u32 spl_boot_mode(const u32 boot_device)
}
#endif
-void spl_disable_firewall_l4_per(void)
-{
- const struct socfpga_firwall_l4_per *firwall_l4_per_base =
- (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
- u32 i;
- const u32 *addr[] = {
- &firwall_l4_per_base->nand,
- &firwall_l4_per_base->nand_data,
- &firwall_l4_per_base->usb0,
- &firwall_l4_per_base->usb1,
- &firwall_l4_per_base->spim0,
- &firwall_l4_per_base->spim1,
- &firwall_l4_per_base->emac0,
- &firwall_l4_per_base->emac1,
- &firwall_l4_per_base->emac2,
- &firwall_l4_per_base->sdmmc,
- &firwall_l4_per_base->gpio0,
- &firwall_l4_per_base->gpio1,
- &firwall_l4_per_base->i2c0,
- &firwall_l4_per_base->i2c1,
- &firwall_l4_per_base->i2c2,
- &firwall_l4_per_base->i2c3,
- &firwall_l4_per_base->i2c4,
- &firwall_l4_per_base->timer0,
- &firwall_l4_per_base->timer1,
- &firwall_l4_per_base->uart0,
- &firwall_l4_per_base->uart1
- };
-
- /*
- * The following lines of code will enable non-secure access
- * to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This
- * is needed as most OS run in non-secure mode. Thus we need to
- * enable non-secure access to these peripherals in order for the
- * OS to use these peripherals.
- */
- for (i = 0; i < ARRAY_SIZE(addr); i++)
- writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
-}
-
-void spl_disable_firewall_l4_sys(void)
-{
- const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
- (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
- u32 i;
- const u32 *addr[] = {
- &firwall_l4_sys_base->dma_ecc,
- &firwall_l4_sys_base->emac0rx_ecc,
- &firwall_l4_sys_base->emac0tx_ecc,
- &firwall_l4_sys_base->emac1rx_ecc,
- &firwall_l4_sys_base->emac1tx_ecc,
- &firwall_l4_sys_base->emac2rx_ecc,
- &firwall_l4_sys_base->emac2tx_ecc,
- &firwall_l4_sys_base->nand_ecc,
- &firwall_l4_sys_base->nand_read_ecc,
- &firwall_l4_sys_base->nand_write_ecc,
- &firwall_l4_sys_base->ocram_ecc,
- &firwall_l4_sys_base->sdmmc_ecc,
- &firwall_l4_sys_base->usb0_ecc,
- &firwall_l4_sys_base->usb1_ecc,
- &firwall_l4_sys_base->clock_manager,
- &firwall_l4_sys_base->io_manager,
- &firwall_l4_sys_base->reset_manager,
- &firwall_l4_sys_base->system_manager,
- &firwall_l4_sys_base->watchdog0,
- &firwall_l4_sys_base->watchdog1,
- &firwall_l4_sys_base->watchdog2,
- &firwall_l4_sys_base->watchdog3
- };
-
- for (i = 0; i < ARRAY_SIZE(addr); i++)
- writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
-}
-
void board_init_f(ulong dummy)
{
const struct cm_config *cm_default_cfg = cm_get_default_config();
@@ -155,16 +81,7 @@ void board_init_f(ulong dummy)
SYSMGR_WRITEL(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, SYSMGR_DMA);
SYSMGR_WRITEL(SYSMGR_DMAPERIPH_ALL_NS, SYSMGR_DMA_PERIPH);
- spl_disable_firewall_l4_per();
-
- spl_disable_firewall_l4_sys();
-
- /* disable lwsocf2fpga and soc2fpga bridge security */
- writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
- writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
-
- /* disable SMMU security */
- writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
+ firewall_setup();
/* disable ocram security at CCU for non secure access */
clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index 80fcac655e..4d82ed47d0 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -13,7 +13,7 @@
#include <reset.h>
#include "sdram_s10.h"
#include <wait_bit.h>
-#include <asm/arch/firewall_s10.h>
+#include <asm/arch/firewall.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/reset_manager.h>
#include <asm/io.h>
--
2.19.0
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