> Subject: [PATCH v3] imx: support i.MX8QM ROM 7720 a1 board > > Add i.MX8QM ROM 7720a1 board support > > Boot log as below: > U-Boot 2019.10-rc2-00283-g198673d9ab (Aug 30 2019 - 10:26:53 +0200) > > CPU: NXP i.MX8QM RevB A53 at 1200 MHz > > Model: Advantech iMX8QM Qseven series > Board: ROM-7720-A1 4GB > Build: SCFW 65afe5f6 > Boot: SD2 > DRAM: 3.9 GiB > MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 > Loading Environment from MMC... OK > In: serial@5a060000 > Out: serial@5a060000 > Err: serial@5a060000 > Net: eth0: ethernet@5b040000Could not get PHY for FEC1: addr 1 > , eth-1: ethernet@5b050000 > Hit any key to stop autoboot: 0 > > Signed-off-by: Oliver Graute <oliver.gra...@kococonnector.com> > Cc: Stefano Babic <sba...@denx.de> > Cc: Fabio Estevam <feste...@gmail.com> > Cc: Peng Fan <peng....@nxp.com> > Cc: Simon Glass <s...@chromium.org> > Cc: Ye Li <ye...@nxp.com> > Cc: uboot-imx <uboot-...@nxp.com> > --- > > These changes are based on this vendor tree: > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub. > com%2FADVANTECH-Corp%2Fuboot-imx6.git&data=02%7C01%7Cpeng.f > an%40nxp.com%7C350e8928b13b4e10ff2b08d72d2eaa59%7C686ea1d3bc2b > 4c6fa92cd99c5c301635%7C0%7C0%7C637027550778709853&sdata=X > P0h%2F%2FjkYM%2BQJ7kmUBKcttxkFLICSZ3KcDL7ITmH6S8%3D&reser > ved=0 > > I adapted the files and compared them with code from similar imx8qm-mek > board > > Changes for v3: > - removed duplicate build_info > - removed CONFIG_FSL_ESDHC > > Changes for v2: > - cleanup of u-boot environment > - set power mode SC_R_DC_0 for full boot of linux kernel > - enabled usdhc2 > - enabled FEC defines > - updated README.md > - enabled readwrite for nfs rootfs > - removed include of environment header > > arch/arm/dts/Makefile | 1 + > arch/arm/dts/imx8qm-rom7720-a1.dts | 373 > ++++++++++++++++++ > arch/arm/mach-imx/imx8/Kconfig | 7 + > arch/arm/mach-imx/mkimage_fit_atf.sh | 3 + > board/freescale/imx8qm_rom7720_a1/Kconfig | 14 + > board/freescale/imx8qm_rom7720_a1/MAINTAINERS | 6 + > board/freescale/imx8qm_rom7720_a1/Makefile | 11 + > board/freescale/imx8qm_rom7720_a1/README | 70 ++++ > .../imx8qm_rom7720_a1/imx8qm_rom7720_a1.c | 168 ++++++++ > .../freescale/imx8qm_rom7720_a1/imximage.cfg | 21 + > board/freescale/imx8qm_rom7720_a1/spl.c | 228 +++++++++++ > configs/imx8qm_rom7720_a1_4G_defconfig | 82 ++++ > include/configs/imx8qm_rom7720.h | 188 +++++++++ > 13 files changed, 1172 insertions(+) > create mode 100644 arch/arm/dts/imx8qm-rom7720-a1.dts > create mode 100644 board/freescale/imx8qm_rom7720_a1/Kconfig > create mode 100644 board/freescale/imx8qm_rom7720_a1/MAINTAINERS > create mode 100644 board/freescale/imx8qm_rom7720_a1/Makefile > create mode 100644 board/freescale/imx8qm_rom7720_a1/README > create mode 100644 > board/freescale/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c > create mode 100644 board/freescale/imx8qm_rom7720_a1/imximage.cfg > create mode 100644 board/freescale/imx8qm_rom7720_a1/spl.c > create mode 100644 configs/imx8qm_rom7720_a1_4G_defconfig > create mode 100644 include/configs/imx8qm_rom7720.h > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index > 0b314c12dd..67340f8a0c 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -635,6 +635,7 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb > dtb-$(CONFIG_ARCH_IMX8) += \ > fsl-imx8qm-apalis.dtb \ > fsl-imx8qm-mek.dtb \ > + imx8qm-rom7720-a1.dtb \ > fsl-imx8qxp-colibri.dtb \ > fsl-imx8qxp-mek.dtb > > diff --git a/arch/arm/dts/imx8qm-rom7720-a1.dts > b/arch/arm/dts/imx8qm-rom7720-a1.dts > new file mode 100644 > index 0000000000..5f9ac955ed > --- /dev/null > +++ b/arch/arm/dts/imx8qm-rom7720-a1.dts > @@ -0,0 +1,373 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * Copyright 2017 NXP > + */ > + > +/dts-v1/; > + > +/* First 128KB is for PSCI ATF. */ > +/memreserve/ 0x80000000 0x00020000; > + > +#include "fsl-imx8qm.dtsi" > + > +/ { > + model = "Advantech iMX8QM Qseven series"; > + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; > + > + chosen { > + bootargs = "console=ttyLP0,115200 > earlycon=lpuart32,0x5a060000,115200"; > + stdout-path = &lpuart0; > + }; > + > + leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_gpio_leds>; > + user { > + label = "heartbeat"; > + gpios = <&gpio2 15 0>; > + default-state = "on"; > + linux,default-trigger = "heartbeat"; > + }; > + }; > + > + regulators { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + reg_usb_otg1_vbus: regulator@0 { > + compatible = "regulator-fixed"; > + reg = <0>; > + regulator-name = "usb_otg1_vbus"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + reg_usdhc2_vmmc: usdhc2_vmmc { > + compatible = "regulator-fixed"; > + regulator-name = "sw-3p3-sd1"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + }; > +}; > + > +&iomuxc { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_hog_1>; > + > + imx8qm-mek { > + pinctrl_hog_1: hoggrp-1 { > + fsl,pins = < > + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 > 0x06000048 > + >; > + }; > + > + pinctrl_fec1: fec1grp { > + fsl,pins = < > + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD > 0x000014a0 > + SC_P_ENET0_MDC_CONN_ENET0_MDC > 0x06000048 > + SC_P_ENET0_MDIO_CONN_ENET0_MDIO > 0x06000048 > + > SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL > 0x00000060 > + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC > 0x00000060 > + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 > 0x00000060 > + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 > 0x00000060 > + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 > 0x00000060 > + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 > 0x00000060 > + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC > 0x00000060 > + > SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL > 0x00000060 > + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 > 0x00000060 > + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 > 0x00000060 > + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 > 0x00000060 > + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 > 0x00000060 > + >; > + }; > + > + pinctrl_fec2: fec2grp { > + fsl,pins = < > + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD > 0x000014a0 > + > SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL > 0x00000060 > + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC > 0x00000060 > + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 > 0x00000060 > + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 > 0x00000060 > + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 > 0x00000060 > + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 > 0x00000060 > + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC > 0x00000060 > + > SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL > 0x00000060 > + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 > 0x00000060 > + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 > 0x00000060 > + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 > 0x00000060 > + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 > 0x00000060 > + >; > + }; > + > + pinctrl_lpuart0: lpuart0grp { > + fsl,pins = < > + SC_P_UART0_RX_DMA_UART0_RX > 0x06000020 > + SC_P_UART0_TX_DMA_UART0_TX > 0x06000020 > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + SC_P_EMMC0_CLK_CONN_EMMC0_CLK > 0x06000041 > + SC_P_EMMC0_CMD_CONN_EMMC0_CMD > 0x00000021 > + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 > 0x00000021 > + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 > 0x00000021 > + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 > 0x00000021 > + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 > 0x00000021 > + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 > 0x00000021 > + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 > 0x00000021 > + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 > 0x00000021 > + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 > 0x00000021 > + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE > 0x06000041 > + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B > 0x00000021 > + >; > + }; > + > + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { > + fsl,pins = < > + SC_P_EMMC0_CLK_CONN_EMMC0_CLK > 0x06000040 > + SC_P_EMMC0_CMD_CONN_EMMC0_CMD > 0x00000020 > + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 > 0x00000020 > + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 > 0x00000020 > + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 > 0x00000020 > + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 > 0x00000020 > + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 > 0x00000020 > + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 > 0x00000020 > + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 > 0x00000020 > + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 > 0x00000020 > + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE > 0x06000040 > + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B > 0x00000020 > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { > + fsl,pins = < > + SC_P_EMMC0_CLK_CONN_EMMC0_CLK > 0x06000040 > + SC_P_EMMC0_CMD_CONN_EMMC0_CMD > 0x00000020 > + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 > 0x00000020 > + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 > 0x00000020 > + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 > 0x00000020 > + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 > 0x00000020 > + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 > 0x00000020 > + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 > 0x00000020 > + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 > 0x00000020 > + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 > 0x00000020 > + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE > 0x06000040 > + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B > 0x00000020 > + >; > + }; > + > + pinctrl_usdhc2_gpio: usdhc2grpgpio { > + fsl,pins = < > + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 > 0x00000021 > + SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 > 0x00000021 > + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 > 0x00000021 > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = < > + SC_P_USDHC1_CLK_CONN_USDHC1_CLK > 0x06000041 > + SC_P_USDHC1_CMD_CONN_USDHC1_CMD > 0x00000021 > + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 > 0x00000021 > + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 > 0x00000021 > + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 > 0x00000021 > + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 > 0x00000021 > + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT > 0x00000021 > + >; > + }; > + > + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { > + fsl,pins = < > + SC_P_USDHC1_CLK_CONN_USDHC1_CLK > 0x06000040 > + SC_P_USDHC1_CMD_CONN_USDHC1_CMD > 0x00000020 > + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 > 0x00000020 > + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 > 0x00000020 > + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 > 0x00000020 > + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 > 0x00000020 > + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT > 0x00000020 > + >; > + }; > + > + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { > + fsl,pins = < > + SC_P_USDHC1_CLK_CONN_USDHC1_CLK > 0x06000040 > + SC_P_USDHC1_CMD_CONN_USDHC1_CMD > 0x00000020 > + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 > 0x00000020 > + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 > 0x00000020 > + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 > 0x00000020 > + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 > 0x00000020 > + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT > 0x00000020 > + >; > + }; > + > + pinctrl_usdhc3: usdhc3grp { > + fsl,pins = < > + SC_P_USDHC2_CLK_CONN_USDHC2_CLK > 0x06000041 > + SC_P_USDHC2_CMD_CONN_USDHC2_CMD > 0x00000021 > + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 > 0x00000021 > + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 > 0x00000021 > + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 > 0x00000021 > + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 > 0x00000021 > + /* WP */ > + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 > 0x00000021 > + /* CD */ > + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 > 0x00000021 > + >; > + }; > + > + pinctrl_lpi2c1: lpi2c1grp { > + fsl,pins = < > + SC_P_GPT0_CLK_DMA_I2C1_SCL > 0x06000020 > + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA > 0x06000020 > + /* > + * Change the default alt function from SCL/SDA > to > others, > + * to avoid select input conflict with GPT0 > + */ > + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 > 0x0700004c > + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 > 0x0700004c > + SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 > 0x0700004c > + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 > 0x0700004c > + >; > + }; > + > + pinctrl_gpio_leds: gpioledsgrp { > + fsl,pins = < > + SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 > 0x00000021 > + >; > + }; > + }; > +}; > + > +&gpio2 { > + status = "okay"; > +}; > + > +&gpio4 { > + status = "okay"; > +}; > + > +&gpio5 { > + status = "okay"; > +}; > + > +&usdhc1 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc1>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > + bus-width = <8>; > + non-removable; > + status = "okay"; > +}; > + > +&usdhc2 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; > + bus-width = <4>; > + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; > + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; > + vmmc-supply = <®_usdhc2_vmmc>; > + status = "okay"; > +}; > + > +&usdhc3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usdhc3>; > + bus-width = <4>; > + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; > + wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; > + status = "okay"; > +}; > + > +&fec1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_fec1>; > + phy-mode = "rgmii"; > + phy-handle = <ðphy0>; > + fsl,ar8031-phy-fixup; > + fsl,magic-packet; > + status = "okay"; > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethphy0: ethernet-phy@0 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <0>; > + }; > + > + ethphy1: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + }; > + }; > +}; > + > +&fec2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_fec2>; > + phy-mode = "rgmii"; > + phy-handle = <ðphy1>; > + fsl,ar8031-phy-fixup; > + fsl,magic-packet; > + status = "okay"; > +}; > + > +&i2c1 { > + #address-cells = <1>; > + #size-cells = <0>; > + clock-frequency = <100000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_lpi2c1>; > + status = "okay"; > + > + pca9557_a: gpio@18 { > + compatible = "nxp,pca9557"; > + reg = <0x18>; > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > + pca9557_b: gpio@19 { > + compatible = "nxp,pca9557"; > + reg = <0x19>; > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > + pca9557_c: gpio@1b { > + compatible = "nxp,pca9557"; > + reg = <0x1b>; > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > + pca9557_d: gpio@1f { > + compatible = "nxp,pca9557"; > + reg = <0x1f>; > + gpio-controller; > + #gpio-cells = <2>; > + }; > +}; > + > +&lpuart0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_lpuart0>; > + status = "okay"; > +}; > + > +&lpuart1 { > + status = "okay"; > +}; > diff --git a/arch/arm/mach-imx/imx8/Kconfig > b/arch/arm/mach-imx/imx8/Kconfig index bbe323d5ca..09b985884f 100644 > --- a/arch/arm/mach-imx/imx8/Kconfig > +++ b/arch/arm/mach-imx/imx8/Kconfig > @@ -42,6 +42,12 @@ config TARGET_IMX8QM_MEK > select BOARD_LATE_INIT > select IMX8QM > > +config TARGET_IMX8QM_ROM7720_A1 > + bool "Support i.MX8QM ROM-7720-A1" > + select BOARD_LATE_INIT > + select SUPPORT_SPL > + select IMX8QM > + > config TARGET_IMX8QXP_MEK > bool "Support i.MX8QXP MEK board" > select BOARD_LATE_INIT > @@ -50,6 +56,7 @@ config TARGET_IMX8QXP_MEK endchoice > > source "board/freescale/imx8qm_mek/Kconfig" > +source "board/freescale/imx8qm_rom7720_a1/Kconfig" > source "board/freescale/imx8qxp_mek/Kconfig" > source "board/toradex/apalis-imx8/Kconfig" > source "board/toradex/colibri-imx8x/Kconfig" > diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh > b/arch/arm/mach-imx/mkimage_fit_atf.sh > index 38c9858e84..75ac8e7ed2 100755 > --- a/arch/arm/mach-imx/mkimage_fit_atf.sh > +++ b/arch/arm/mach-imx/mkimage_fit_atf.sh > @@ -19,6 +19,9 @@ else > ls -lct $BL31 | awk '{print $5}' >&2 > fi > > +echo "ATF_LOAD_ADDR=$ATF_LOAD_ADDR" >&2 echo > +"BL33_LOAD_ADDR=$BL33_LOAD_ADDR" >&2 > +
This is no needed. > BL32="tee.bin" > > if [ ! -f $BL32 ]; then > diff --git a/board/freescale/imx8qm_rom7720_a1/Kconfig > b/board/freescale/imx8qm_rom7720_a1/Kconfig > new file mode 100644 > index 0000000000..7041567d44 > --- /dev/null > +++ b/board/freescale/imx8qm_rom7720_a1/Kconfig > @@ -0,0 +1,14 @@ > +if TARGET_IMX8QM_ROM7720_A1 > + > +config SYS_BOARD > + default "imx8qm_rom7720_a1" > + > +config SYS_VENDOR > + default "freescale" This board is not from nxp(freescale). Please correct vendor. > + > +config SYS_CONFIG_NAME > + default "imx8qm_rom7720" > + > +source "board/freescale/common/Kconfig" > + > +endif > diff --git a/board/freescale/imx8qm_rom7720_a1/MAINTAINERS > b/board/freescale/imx8qm_rom7720_a1/MAINTAINERS > new file mode 100644 > index 0000000000..c5553d5ad9 > --- /dev/null > +++ b/board/freescale/imx8qm_rom7720_a1/MAINTAINERS > @@ -0,0 +1,6 @@ > +i.MX8QM ROM 7720 a1 BOARD > +M: Oliver Graute <oliver.gra...@kococonnector.com> > +S: Maintained > +F: board/freescale/imx8qm_rom7720_a1/ > +F: include/configs/imx8qm_rom7720.h > +F: configs/imx8qm_rom7720_a1_4G_defconfig > diff --git a/board/freescale/imx8qm_rom7720_a1/Makefile > b/board/freescale/imx8qm_rom7720_a1/Makefile > new file mode 100644 > index 0000000000..51c5de251c > --- /dev/null > +++ b/board/freescale/imx8qm_rom7720_a1/Makefile > @@ -0,0 +1,11 @@ > +# > +# Copyright 2017 NXP > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y += imx8qm_rom7720_a1.o > + > +ifdef CONFIG_SPL_BUILD > +obj-y += spl.o > +endif > diff --git a/board/freescale/imx8qm_rom7720_a1/README > b/board/freescale/imx8qm_rom7720_a1/README > new file mode 100644 > index 0000000000..eabca8b07a > --- /dev/null > +++ b/board/freescale/imx8qm_rom7720_a1/README > @@ -0,0 +1,70 @@ > +U-Boot for the NXP i.MX8QM ROM 7720a1 board > + > +Quick Start > +=========== > + > +- Build the ARM Trusted firmware binary > +- Get scfw_tcm.bin and ahab-container.img > +- Get imx-mkimage > +- Build U-Boot > +- Build imx-mkimage > +- Flash the binary into the SD card > +- Boot > + > +Get and Build the ARM Trusted firmware > +====================================== > + > +$ git clone > +https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsourc > +e.codeaurora.org%2Fexternal%2Fimx%2Fimx-atf&data=02%7C01%7Cp > eng.fan > +%40nxp.com%7C350e8928b13b4e10ff2b08d72d2eaa59%7C686ea1d3bc2b4 > c6fa92cd99 > +c5c301635%7C0%7C0%7C637027550778719850&sdata=Kev7P70hgms > ekgjh9WliyM > +vipwvYnDIOVFNlAwQ4GhM%3D&reserved=0 > +$ cd imx-atf/ > +$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga $ > +make PLAT=imx8qm bl31 > + > +Get scfw_tcm.bin and ahab-container.img > ============================== > + > +$ wget > +https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww > .n > +xp.com%2Flgfiles%2FNMG%2FMAD%2FYOCTO%2Fimx-sc-firmware-1.1.bin > &data > +=02%7C01%7Cpeng.fan%40nxp.com%7C350e8928b13b4e10ff2b08d72d2ea > a59%7C686e > +a1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637027550778719850&a > mp;sdata=I3g > +2%2B%2FsyadeaLLaRBlFtAuvrWHPT85kpkQetwrw6NNk%3D&reserved > =0 > +$ chmod +x imx-sc-firmware-1.1.bin > +$ ./imx-sc-firmware-1.1.bin > +$ wget > +https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww > .n > +xp.com%2Flgfiles%2FNMG%2FMAD%2FYOCTO%2Ffirmware-imx-8.0.bin&a > mp;data=02 > +%7C01%7Cpeng.fan%40nxp.com%7C350e8928b13b4e10ff2b08d72d2eaa59 > %7C686ea1d > +3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637027550778719850&s > data=YiHH7n > +1xedwyoNxGtw4Ne8Dl0P7xgK6ZFOEx2rJcgMM%3D&reserved=0 > +$ chmod +x firmware-imx-8.0.bin > +$ ./firmware-imx-8.0.bin > + > +Build U-Boot > +============ > + > +$ export ATF_LOAD_ADDR=0x80000000 > +$ export BL33_LOAD_ADDR=0x80020000 > +$ make imx8qm_rom7720_a1_4G_defconfig > +$ make flash.bin > +$ dd if=u-boot.itb of=flash.bin bs=512 seek=854 > + > +Get imx-mkimage > +============================== > + > +$ git clone > +https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsourc > +e.codeaurora.org%2Fexternal%2Fimx%2Fimx-mkimage%2F&data=02% > 7C01%7Cp > +eng.fan%40nxp.com%7C350e8928b13b4e10ff2b08d72d2eaa59%7C686ea1d > 3bc2b4c6f > +a92cd99c5c301635%7C0%7C0%7C637027550778719850&sdata=nV2 > %2FaSmJZDL2J > +F6mJhW8jlSVGAMNJoQBCIBEem%2F5BRs%3D&reserved=0 > +$ cd imx-mkimage > +$ git checkout rel_imx_4.14.78_1.0.0_ga -b rel_imx_4.14.78_1.0.0_ga $ > +cd iMX8QM/ > + > +Copy the following binaries to iMX8QM folder: > + > +$ cp imx-atf/build/imx8qm/release/bl31.bin . > +$ cp u-boot/u-boot.bin . > + > +Copy the following firmwares U-Boot folder : > + > +$ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img . > +$ cp imx-sc-firmware-1.1/mx8qm-val-scfw-tcm.bin scfw_tcm.bin > + > +$ make SOC=iMX8QM flash_linux_m4 flash_linux_m4 is not a valid build target in U-Boot. > + > +Flash the binary into the SD card > +================================= > + > +Burn the flash.bin binary to SD card offset 32KB: > + > +$ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync > + > +Boot > +==== > +Set Boot switch SW2: 1100. > diff --git a/board/freescale/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c > b/board/freescale/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c > new file mode 100644 > index 0000000000..7fce367cb4 > --- /dev/null > +++ b/board/freescale/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c > @@ -0,0 +1,168 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2017-2018 NXP > + * Copyright (C) 2019 Oliver Graute <oliver.gra...@kococonnector.com> > +*/ > + > +#include <common.h> > +#include <errno.h> > +#include <linux/libfdt.h> > +#include <asm/io.h> > +#include <asm/gpio.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/sci/sci.h> > +#include <asm/arch/imx8-pins.h> > +#include <asm/arch/iomux.h> > +#include <asm/arch/sys_proto.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << > PADRING_CONFIG_SHIFT) | \ > + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ > + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | > \ > + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) > + > +static iomux_cfg_t uart0_pads[] = { > + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), > + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; > + > +static void setup_iomux_uart(void) > +{ > + imx8_iomux_setup_multiple_pads(uart0_pads, > ARRAY_SIZE(uart0_pads)); } > + > +int board_early_init_f(void) > +{ > + int ret; > + /* Set UART0 clock root to 80 MHz */ > + sc_pm_clock_rate_t rate = 80000000; > + > + /* Power up UART0 */ > + ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, > SC_PM_PW_MODE_ON); > + if (ret) > + return ret; > + > + ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); > + if (ret) > + return ret; > + > + /* Enable UART0 clock root */ > + ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); > + if (ret) > + return ret; Please use sc_pm_setup_uart > + > + setup_iomux_uart(); > + > + sc_pm_set_resource_power_mode(-1, SC_R_DC_0, > SC_PM_PW_MODE_ON); Why power up DC_0? Should not kernel do it by itself? > + sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, > SC_PM_PW_MODE_ON); > + > + return 0; > +} > + > +#if IS_ENABLED(CONFIG_DM_GPIO) > +static void board_gpio_init(void) > +{ > + /* TODO */ > +} > +#else > +static inline void board_gpio_init(void) {} #endif If do nothing, please drop. > + > +#if IS_ENABLED(CONFIG_FEC_MXC) > +#include <miiphy.h> > + > +int board_phy_config(struct phy_device *phydev) { #ifdef > +CONFIG_FEC_ENABLE_MAX7322 > + u8 value; > + > + /* This is needed to drive the pads to 1.8V instead of 1.5V */ > + i2c_set_bus_num(CONFIG_MAX7322_I2C_BUS); > + > + if (!i2c_probe(CONFIG_MAX7322_I2C_ADDR)) { > + /* Write 0x1 to enable O0 output, this device has no addr */ > + /* hence addr length is 0 */ > + value = 0x1; > + if (i2c_write(CONFIG_MAX7322_I2C_ADDR, 0, 0, &value, 1)) > + printf("MAX7322 write failed\n"); > + } else { > + printf("MAX7322 Not found\n"); > + } > + mdelay(1); Please use DM_I2C. > +#endif > + > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); > + > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); > + > + if (phydev->drv->config) > + phydev->drv->config(phydev); > + > + return 0; > +} > +#endif > + > +int checkboard(void) > +{ > + puts("Board: ROM-7720-A1 4GB\n"); > + > + build_info(); > + print_bootinfo(); > + > + return 0; > +} > + > +int board_init(void) > +{ > + /* Power up base board */ > + sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, > SC_PM_PW_MODE_ON); > + > + board_gpio_init(); > + > + return 0; > +} > + > +void detail_board_ddr_info(void) > +{ > + puts("\nDDR "); > +} > + > +/* > + * Board specific reset that is system reset. > + */ > +void reset_cpu(ulong addr) > +{ > + /* TODO */ > +} > + > +#ifdef CONFIG_OF_BOARD_SETUP > +int ft_board_setup(void *blob, bd_t *bd) { > + return 0; > +} > +#endif Drop it do nothing. > + > +int board_mmc_get_env_dev(int devno) > +{ > + return devno; > +} > + > +int board_late_init(void) > +{ > +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG > + env_set("board_name", "ROM-7720-A1"); > + env_set("board_rev", "iMX8QM"); > +#endif > + > + env_set("sec_boot", "no"); > +#ifdef CONFIG_AHAB_BOOT > + env_set("sec_boot", "yes"); > +#endif > + > + return 0; > +} > diff --git a/board/freescale/imx8qm_rom7720_a1/imximage.cfg > b/board/freescale/imx8qm_rom7720_a1/imximage.cfg > new file mode 100644 > index 0000000000..e324c7ca37 > --- /dev/null > +++ b/board/freescale/imx8qm_rom7720_a1/imximage.cfg > @@ -0,0 +1,21 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright 2018 NXP > + */ > + > +#define __ASSEMBLY__ > + > +/* Boot from SD, sector size 0x400 */ > +BOOT_FROM SD 0x400 > +/* SoC type IMX8QM */ > +SOC_TYPE IMX8QM > +/* Append seco container image */ > +APPEND mx8qm-ahab-container.img > +/* Create the 2nd container */ > +CONTAINER > +/* Add scfw image with exec attribute */ IMAGE SCU > +mx8qm-val-scfw-tcm.bin > +/* Add ATF image with exec attribute */ IMAGE A35 bl31.bin 0x80000000 > +/* Add U-Boot image with load attribute */ DATA A35 u-boot-dtb.bin > +0x80020000 > diff --git a/board/freescale/imx8qm_rom7720_a1/spl.c > b/board/freescale/imx8qm_rom7720_a1/spl.c > new file mode 100644 > index 0000000000..2888d0661c > --- /dev/null > +++ b/board/freescale/imx8qm_rom7720_a1/spl.c > @@ -0,0 +1,228 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2017-2018 NXP > + */ > +#include <common.h> > +#include <dm.h> > +#include <spl.h> > +#include <fsl_esdhc.h> > + > +#include <asm/io.h> > +#include <asm/gpio.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/sci/sci.h> > +#include <asm/arch/imx8-pins.h> > +#include <asm/arch/iomux.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << > PADRING_CONFIG_SHIFT) | \ > + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ > + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ > + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) > + > +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << > PADRING_CONFIG_SHIFT) | \ > + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ > + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ > + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) > + > +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << > PADRING_CONFIG_SHIFT) | \ > + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ > + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ > + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) > + > +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << > PADRING_CONFIG_SHIFT) | \ > + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ > + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ > + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) > + > +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << > PADRING_CONFIG_SHIFT) | \ > + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ > + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ > + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) > + > +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << > PADRING_CONFIG_SHIFT) | \ > + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ > + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ > + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) > + > +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << > PADRING_CONFIG_SHIFT) | \ > + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ > + (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \ > + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) > + > +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << > PADRING_CONFIG_SHIFT) | \ > + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ > + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ > + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) #ifdef > CONFIG_FSL_ESDHC > + > +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22) > +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12) > + > +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { > + {USDHC1_BASE_ADDR, 0, 8}, > + {USDHC2_BASE_ADDR, 0, 4}, > + {USDHC3_BASE_ADDR, 0, 4}, > +}; > + > +static iomux_cfg_t emmc0[] = { > + SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), > + SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), > + SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), > + SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), > + SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), > + SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), > + SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), > + SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), > + SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), > + SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), > + SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), > + SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL), }; > + > +static iomux_cfg_t usdhc2_sd[] = { > + SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), > + SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), > + SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), > + SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), > + SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), > + SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), > + SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), > + SC_P_USDHC2_WP | MUX_MODE_ALT(3) | > MUX_PAD_CTRL(ESDHC_PAD_CTRL), > + SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | > MUX_PAD_CTRL(ESDHC_PAD_CTRL), }; > + > +int board_mmc_init(bd_t *bis) > +{ > + int i, ret; > + > + /* > + * According to the board_mmc_init() the following map is done: > + * (U-Boot device node) (Physical Port) > + * mmc0 USDHC1 > + * mmc1 USDHC2 > + * mmc2 USDHC3 > + */ > + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { > + switch (i) { > + case 0: > + ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, > SC_PM_PW_MODE_ON); > + if (ret != SC_ERR_NONE) > + return ret; > + > + imx8_iomux_setup_multiple_pads(emmc0, > ARRAY_SIZE(emmc0)); > + init_clk_usdhc(0); > + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); > + break; > + case 1: > + ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, > SC_PM_PW_MODE_ON); > + if (ret != SC_ERR_NONE) > + return ret; > + ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, > SC_PM_PW_MODE_ON); > + if (ret != SC_ERR_NONE) > + return ret; > + > + imx8_iomux_setup_multiple_pads(usdhc2_sd, > ARRAY_SIZE(usdhc2_sd)); > + init_clk_usdhc(2); > + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); > + gpio_request(USDHC2_CD_GPIO, "sd2_cd"); > + gpio_direction_input(USDHC2_CD_GPIO); > + break; > + default: > + printf("Warning: you configured more USDHC controllers" > + "(%d) than supported by the board\n", i + 1); > + return 0; > + } > + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); > + if (ret) { > + printf("Warning: failed to initialize mmc dev %d\n", i); > + return ret; > + } > + } > + > + return 0; > +} > + > +int board_mmc_getcd(struct mmc *mmc) > +{ > + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; > + int ret = 0; > + > + switch (cfg->esdhc_base) { > + case USDHC1_BASE_ADDR: > + ret = 1; > + break; > + case USDHC2_BASE_ADDR: > + ret = !gpio_get_value(USDHC1_CD_GPIO); > + break; > + case USDHC3_BASE_ADDR: > + ret = !gpio_get_value(USDHC2_CD_GPIO); > + break; > + } > + > + return ret; > +} SPL_DM_MMC should help. > + > +#endif /* CONFIG_FSL_ESDHC */ > + > +void spl_dram_init(void) > +{ > + /* do nothing for now */ > +} Drop > + > +void spl_board_init(void) > +{ > +#if defined(CONFIG_SPL_SPI_SUPPORT) > + if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) { > + if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, > SC_PM_PW_MODE_ON)) { > + puts("Warning: failed to initialize FSPI0\n"); > + } > + } > +#endif > + > + /* DDR initialization */ > + spl_dram_init(); > + > + puts("Normal Boot\n"); > +} > + > +void spl_board_prepare_for_boot(void) > +{ > +#if defined(CONFIG_SPL_SPI_SUPPORT) > + if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) { > + if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, > SC_PM_PW_MODE_OFF)) { > + puts("Warning: failed to turn off FSPI0\n"); > + } > + } > +#endif > +} > + > +#ifdef CONFIG_SPL_LOAD_FIT > +int board_fit_config_name_match(const char *name) { > + /* Just empty function now - can't decide what to choose */ > + debug("%s: %s\n", __func__, name); > + > + return 0; > +} > +#endif > + > +void board_init_f(ulong dummy) > +{ > + /* Clear global data */ > + memset((void *)gd, 0, sizeof(gd_t)); > + > + arch_cpu_init(); > + > + board_early_init_f(); > + > + timer_init(); > + > + preloader_console_init(); > + > + /* Clear the BSS. */ > + memset(__bss_start, 0, __bss_end - __bss_start); > + > + board_init_r(NULL, 0); > +} > diff --git a/configs/imx8qm_rom7720_a1_4G_defconfig > b/configs/imx8qm_rom7720_a1_4G_defconfig > new file mode 100644 > index 0000000000..0384bfca48 > --- /dev/null > +++ b/configs/imx8qm_rom7720_a1_4G_defconfig > @@ -0,0 +1,82 @@ > +CONFIG_ARM=y > +CONFIG_SPL_SYS_ICACHE_OFF=y > +CONFIG_SPL_SYS_DCACHE_OFF=y > +CONFIG_ARCH_IMX8=y > +CONFIG_SYS_TEXT_BASE=0x80020000 > +CONFIG_SYS_MALLOC_F_LEN=0x4000 This might not large enough, check how i.MX8QM MEK does in upstream. > +CONFIG_SPL_GPIO_SUPPORT=y > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_TARGET_IMX8QM_ROM7720_A1=y > +CONFIG_SPL_MMC_SUPPORT=y > +CONFIG_SPL_SERIAL_SUPPORT=y > +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y > +CONFIG_NR_DRAM_BANKS=4 > +CONFIG_SPL=y > +CONFIG_FIT=y > +CONFIG_SPL_LOAD_FIT=y > +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" > +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_ro > m7720_a1/imximage.cfg" > +CONFIG_BOOTDELAY=3 > +CONFIG_LOG=y > +CONFIG_BOARD_EARLY_INIT_F=y > +CONFIG_SPL_BOARD_INIT=y > +CONFIG_HUSH_PARSER=y > +CONFIG_SPL_SEPARATE_BSS=y > +CONFIG_SPL_POWER_SUPPORT=y > +CONFIG_SPL_POWER_DOMAIN=y > +CONFIG_SPL_WATCHDOG_SUPPORT=y > +CONFIG_CMD_CPU=y > +# CONFIG_CMD_IMPORTENV is not set > +CONFIG_CMD_CLK=y > +CONFIG_CMD_DM=y > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_I2C=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_DHCP=y > +CONFIG_CMD_MII=y > +CONFIG_CMD_PING=y > +CONFIG_CMD_CACHE=y > +CONFIG_CMD_FAT=y > +CONFIG_SPL_OF_CONTROL=y > +CONFIG_DEFAULT_DEVICE_TREE="imx8qm-rom7720-a1" > +CONFIG_ENV_IS_IN_MMC=y > +CONFIG_SPL_DM=y > +CONFIG_SPL_CLK=y > +CONFIG_CLK_IMX8=y > +CONFIG_CPU=y > +CONFIG_DM_GPIO=y > +CONFIG_MXC_GPIO=y > +CONFIG_DM_PCA953X=y > +CONFIG_DM_I2C=y > +CONFIG_SYS_I2C_IMX_LPI2C=y > +CONFIG_I2C_MUX=y > +CONFIG_I2C_MUX_PCA954x=y > +CONFIG_MISC=y > +CONFIG_DM_MMC=y > +CONFIG_FSL_ESDHC_IMX=y > +CONFIG_PHYLIB=y > +CONFIG_PHY_ADDR_ENABLE=y > +CONFIG_PHY_ATHEROS=y > +CONFIG_DM_ETH=y > +CONFIG_PHY_GIGE=y > +CONFIG_FEC_MXC_SHARE_MDIO=y > +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 > +CONFIG_FEC_MXC=y > +CONFIG_MII=y > +CONFIG_PINCTRL=y > +CONFIG_SPL_PINCTRL=y > +CONFIG_PINCTRL_IMX8=y > +CONFIG_POWER_DOMAIN=y > +CONFIG_IMX8_POWER_DOMAIN=y > +CONFIG_DM_REGULATOR=y > +CONFIG_SPL_DM_REGULATOR=y > +CONFIG_DM_REGULATOR_FIXED=y > +CONFIG_DM_REGULATOR_GPIO=y > +CONFIG_SPL_DM_REGULATOR_GPIO=y > +CONFIG_DM_SERIAL=y > +CONFIG_FSL_LPUART=y > +CONFIG_SPL_TINY_MEMSET=y > +# CONFIG_EFI_LOADER is not set > +CONFIG_ARCH_MISC_INIT > +CONFIG_NET_RANDOM_ETHADDR=y > diff --git a/include/configs/imx8qm_rom7720.h > b/include/configs/imx8qm_rom7720.h > new file mode 100644 > index 0000000000..a5c869b94e > --- /dev/null > +++ b/include/configs/imx8qm_rom7720.h Please check how i.MX8QM MEK does in upstream. > @@ -0,0 +1,188 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2017-2018 NXP > + */ > + > +#ifndef __IMX8QM_ROM7720_H > +#define __IMX8QM_ROM7720_H > + > +#include <linux/sizes.h> > +#include <asm/arch/imx-regs.h> > +#define CONFIG_REMAKE_ELF > +/* Flat Device Tree Definitions */ > +#define CONFIG_OF_BOARD_SETUP > + > +#undef CONFIG_BOOTM_NETBSD > + > +#define CONFIG_FSL_USDHC > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 > +#define USDHC1_BASE_ADDR 0x5B010000 > +#define USDHC2_BASE_ADDR 0x5B020000 > +#define USDHC3_BASE_ADDR 0x5B030000 Not needed. > +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ > + > +#define CONFIG_ENV_OVERWRITE > + > +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG > +/* FUSE command */ > +#define CONFIG_CMD_FUSE > + > +#ifdef CONFIG_AHAB_BOOT > +#define AHAB_ENV "sec_boot=yes\0" > +#else > +#define AHAB_ENV "sec_boot=no\0" AHAB not supported currently in upstream. Regards, Peng. > +#endif > + > +/* Boot M4 */ > +#define M4_BOOT_ENV \ > + "m4_0_image=m4_0.bin\0" \ > + "m4_1_image=m4_1.bin\0" \ > + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} > ${m4_0_image}\0" \ > + "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} > ${m4_1_image}\0" \ > + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" > \ > + "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" > \ > + > +#ifdef CONFIG_NAND_BOOT > +#define MFG_NAND_PARTITION > "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " > +#else > +#define MFG_NAND_PARTITION "" > +#endif > + > +#define CONFIG_MFG_ENV_SETTINGS \ > + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ > + "rdinit=/linuxrc " \ > + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ > + "g_mass_storage.idVendor=0x066F > g_mass_storage.idProduct=0x37FF "\ > + "g_mass_storage.iSerialNumber=\"\" "\ > + MFG_NAND_PARTITION \ > + "clk_ignore_unused "\ > + "\0" \ > + "initrd_addr=0x83800000\0" \ > + "initrd_high=0xffffffffffffffff\0" \ > + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} > +${fdt_addr};\0" \ > + > +/* Initial environment variables */ > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + CONFIG_MFG_ENV_SETTINGS \ > + M4_BOOT_ENV \ > + AHAB_ENV \ > + "script=boot.scr\0" \ > + "image=Image\0" \ > + "panel=NULL\0" \ > + "console=ttyLP0\0" \ > + "fdt_addr=0x83000000\0" \ > + "fdt_high=0xffffffffffffffff\0" \ > + "boot_fdt=try\0" \ > + "fdt_file=imx8qm-rom7720-a1.dtb\0" \ > + "initrd_addr=0x83800000\0" \ > + "initrd_high=0xffffffffffffffff\0" \ > + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ > + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ > + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ > + "mmcautodetect=yes\0" \ > + "mmcargs=setenv bootargs console=${console},${baudrate} > root=${mmcroot} earlycon\0 " \ > + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} > ${script};\0" \ > + "bootscript=echo Running bootscript from mmc ...; " \ > + "source\0" \ > + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} > ${image}\0" \ > + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" > \ > + "mmcboot=echo Booting from mmc ...; " \ > + "run mmcargs; " \ > + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ > + "if run loadfdt; then " \ > + "booti ${loadaddr} - ${fdt_addr}; " \ > + "else " \ > + "echo WARN: Cannot load the DT; " \ > + "fi; " \ > + "else " \ > + "echo wait for boot; " \ > + "fi;\0" \ > + "netargs=setenv bootargs console=${console},${baudrate} " \ > + "root=/dev/nfs " \ > + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \ > + "netboot=echo Booting from net ...; " \ > + "run netargs; " \ > + "if test ${ip_dyn} = yes; then " \ > + "setenv get_cmd dhcp; " \ > + "else " \ > + "setenv get_cmd tftp; " \ > + "fi; " \ > + "${get_cmd} ${loadaddr} ${image}; " \ > + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ > + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ > + "booti ${loadaddr} - ${fdt_addr}; " \ > + "else " \ > + "echo WARN: Cannot load the DT; " \ > + "fi; " \ > + "else " \ > + "booti; " \ > + "fi;\0" > + > +#define CONFIG_BOOTCOMMAND \ > + "mmc dev ${mmcdev}; if mmc rescan; then " \ > + "if run loadbootscript; then " \ > + "run bootscript; " \ > + "else " \ > + "if run loadimage; then " \ > + "run mmcboot; " \ > + "else run netboot; " \ > + "fi; " \ > + "fi; " \ > + "else booti ${loadaddr} - ${fdt_addr}; fi" > + > +/* Link Definitions */ > +#define CONFIG_LOADADDR 0x80280000 > + > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR > + > +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 > + > +/* Default environment is in SD */ > +#define CONFIG_ENV_SIZE 0x2000 > + > +#ifdef CONFIG_QSPI_BOOT > +#define CONFIG_ENV_OFFSET (4 * 1024 * 1024) > +#define CONFIG_ENV_SECT_SIZE (128 * 1024) > +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS > +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS > +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE > +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED > +#else > +#define CONFIG_ENV_OFFSET (64 * SZ_64K) > +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ > +#endif > + > +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 > + > +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board, > + * USDHC3 is for SD on base board On DDR4 board, USDHC1 is mux for > +NAND, > + * USDHC2 is for SD, USDHC3 is for SD on base board */ > +#define CONFIG_SYS_MMC_ENV_DEV 2 /* USDHC3 */ > +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 > */ > +#define CONFIG_SYS_FSL_USDHC_NUM 3 > + > +/* Size of malloc() pool */ > +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) > * 1024) > + > +#define CONFIG_SYS_SDRAM_BASE 0x80000000 > +#define PHYS_SDRAM_1 0x80000000 > +#define PHYS_SDRAM_2 0x880000000 > +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ > +/* LPDDR4 board total DDR is 6GB, DDR4 board total DDR is 4 GB */ > +#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ > + > +#define CONFIG_SYS_MEMTEST_START 0xA0000000 > +#define CONFIG_SYS_MEMTEST_END > (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2)) > + > +/* Serial */ > +#define CONFIG_BAUDRATE 115200 > + > +/* Generic Timer Definitions */ > +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ > + > +/* Networking */ > +#define CONFIG_FEC_XCV_TYPE RGMII > +#define FEC_QUIRK_ENET_MAC > + > +#endif /* __IMX8QM_ROM7720_H */ > -- > 2.17.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
