This patch is to add peripheral clock support
Signed-off-by: Yinbo Zhu <yinbo....@nxp.com>
---
.../armv8/fsl-layerscape/fsl_lsch2_speed.c | 49 ++++++++++++-------
.../armv8/fsl-layerscape/fsl_lsch3_speed.c | 45 ++++++++++++++++-
.../asm/arch-fsl-layerscape/immap_lsch2.h | 2 +-
.../asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
4 files changed, 78 insertions(+), 19 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 9ece4b90e6..23391398ed 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -22,10 +22,12 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(struct sys_info *sys_info)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-#if (defined(CONFIG_FSL_ESDHC) &&\
- defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
- defined(CONFIG_SYS_DPAA_FMAN)
-
+/* rcw_tmp is needed to get FMan clock, or to get cluster group A
+ * mux 2 clock for LS1043A/LS1046A.
+ */
+#if defined(CONFIG_SYS_DPAA_FMAN) || \
+ defined(CONFIG_TARGET_LS1046ARDB) || \
+ defined(CONFIG_TARGET_LS1043ARDB)
u32 rcw_tmp;
#endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
@@ -122,32 +124,32 @@ void get_sys_info(struct sys_info *sys_info)
}
#endif
+#ifdef CONFIG_FSL_ESDHC
#define HWA_CGA_M2_CLK_SEL 0x00000007
#define HWA_CGA_M2_CLK_SHIFT 0
-#ifdef CONFIG_FSL_ESDHC
-#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+#if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB)
rcw_tmp = in_be32(&gur->rcwsr[15]);
switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
case 1:
- sys_info->freq_sdhc = freq_c_pll[1];
+ sys_info->freq_cga_m2 = freq_c_pll[1];
break;
+#if defined(CONFIG_TARGET_LS1046ARDB)
case 2:
- sys_info->freq_sdhc = freq_c_pll[1] / 2;
+ sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
break;
+#endif
case 3:
- sys_info->freq_sdhc = freq_c_pll[1] / 3;
+ sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
break;
+#if defined(CONFIG_TARGET_LS1046ARDB)
case 6:
- sys_info->freq_sdhc = freq_c_pll[0] / 2;
+ sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
break;
+#endif
default:
- printf("Error: Unknown ESDHC clock select!\n");
+ printf("Error: Unknown peripheral clock select!\n");
break;
}
-#else
- sys_info->freq_sdhc = (sys_info->freq_systembus /
- CONFIG_SYS_FSL_PCLK_DIV) /
- CONFIG_SYS_FSL_SDHC_CLK_DIV;
#endif
#endif
@@ -183,9 +185,22 @@ int get_clocks(void)
gd->mem_clk = sys_info.freq_ddrbus;
#ifdef CONFIG_FSL_ESDHC
- gd->arch.sdhc_clk = sys_info.freq_sdhc;
+#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
+#if defined(CONFIG_TARGET_LS1046ARDB)
+ gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
+#endif
+#if defined(CONFIG_TARGET_LS1043ARDB)
+ gd->arch.sdhc_clk = sys_info.freq_cga_m2;
+#endif
+#if defined(CONFIG_TARGET_LS1012ARDB)
+ gd->arch.sdhc_clk = sys_info.freq_systembus;
+#endif
+#else
+ gd->arch.sdhc_clk = (sys_info.freq_systembus /
+ CONFIG_SYS_FSL_PCLK_DIV) /
+ CONFIG_SYS_FSL_SDHC_CLK_DIV;
+#endif
#endif
-
if (gd->cpu_clk != 0)
return 0;
else
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index 0985778ff9..c2b11039af 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -63,6 +63,9 @@ void get_sys_info(struct sys_info *sys_info)
};
uint i, cluster;
+#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
+ uint rcw_tmp;
+#endif
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
@@ -126,8 +129,39 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_localbus = sys_info->freq_systembus /
CONFIG_SYS_FSL_IFC_CLK_DIV;
#endif
-}
+#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
+#define HWA_CGA_M2_CLK_SEL 0x00380000
+#define HWA_CGA_M2_CLK_SHIFT 19
+ rcw_tmp = in_le32(&gur->rcwsr[5]);
+ switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
+ case 1:
+ sys_info->freq_cga_m2 = freq_c_pll[1];
+ break;
+ case 2:
+ sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
+ break;
+ case 3:
+ sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
+ break;
+ case 4:
+ sys_info->freq_cga_m2 = freq_c_pll[1] / 4;
+ break;
+ case 6:
+ sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
+ break;
+ case 7:
+ sys_info->freq_cga_m2 = freq_c_pll[0] / 3;
+ break;
+ default:
+ printf("Error: Unknown peripheral clock select!\n");
+ break;
+ }
+#endif
+#if defined(CONFIG_TARGET_LX2160ARDB) || defined(CONFIG_TARGET_LS2080ARDB)
+ sys_info->freq_cga_m2 = sys_info->freq_systembus;
+#endif
+}
int get_clocks(void)
{
@@ -140,7 +174,16 @@ int get_clocks(void)
gd->arch.mem2_clk = sys_info.freq_ddrbus2;
#endif
#if defined(CONFIG_FSL_ESDHC)
+#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
+#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LX2160ARDB)
+ gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
+#endif
+#if defined(CONFIG_TARGET_LS2080ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
+ gd->arch.sdhc_clk = sys_info.freq_cga_m2;
+#endif
+#else
gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
+#endif
#endif /* defined(CONFIG_FSL_ESDHC) */
if (gd->cpu_clk != 0)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index b4b7c3492e..3a59abb10e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -180,7 +180,7 @@ struct sys_info {
unsigned long freq_systembus;
unsigned long freq_ddrbus;
unsigned long freq_localbus;
- unsigned long freq_sdhc;
+ unsigned long freq_cga_m2;
#ifdef CONFIG_SYS_DPAA_FMAN
unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 551bc648c9..5d095319b0 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -264,6 +264,7 @@ struct sys_info {
/* frequency of platform PLL */
unsigned long freq_systembus;
unsigned long freq_ddrbus;
+ unsigned long freq_cga_m2;
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
unsigned long freq_ddrbus2;
#endif
--
2.17.1
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