[U-Boot] [PATCH 2/3] usb: dwc2_udc_otg: add bcm2835 SoC (Raspberry Pi4) support

[Marek Szyprowski]

Broadcom 2835 SoC requires special conversion of physical memory addresses
for DMA purpose, so add needed wrappers to dwc2_udc_otg driver. Also extend
the list of compatible devices with 'brcm,bcm2835-usb' entry. This allows
to use USB gadget drivers (i.e. DFU) on Raspberry Pi4 boards.

Signed-off-by: Marek Szyprowski <m.szyprow...@samsung.com>
---
 drivers/usb/gadget/dwc2_udc_otg.c          |  2 ++
 drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c | 12 ++++++------
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/usb/gadget/dwc2_udc_otg.c 
b/drivers/usb/gadget/dwc2_udc_otg.c
index 35f4147840e..49f342eb211 100644
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -31,6 +31,7 @@
 #include <linux/usb/otg.h>
 #include <linux/usb/gadget.h>
 
+#include <phys2bus.h>
 #include <asm/byteorder.h>
 #include <asm/unaligned.h>
 #include <asm/io.h>
@@ -1213,6 +1214,7 @@ static int dwc2_udc_otg_remove(struct udevice *dev)
 
 static const struct udevice_id dwc2_udc_otg_ids[] = {
        { .compatible = "snps,dwc2" },
+       { .compatible = "brcm,bcm2835-usb" },
        { .compatible = "st,stm32mp1-hsotg",
          .data = (ulong)dwc2_set_stm32mp1_hsotg_params },
        {},
diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c 
b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
index 7eb632d3b14..5e695b4ff2a 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
+++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
@@ -28,7 +28,7 @@ static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev)
 {
        u32 ep_ctrl;
 
-       writel(usb_ctrl_dma_addr, &reg->in_endp[EP0_CON].diepdma);
+       writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), 
&reg->in_endp[EP0_CON].diepdma);
        writel(DIEPT_SIZ_PKT_CNT(1), &reg->in_endp[EP0_CON].dieptsiz);
 
        ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
@@ -49,7 +49,7 @@ static void dwc2_udc_pre_setup(void)
 
        writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
               &reg->out_endp[EP0_CON].doeptsiz);
-       writel(usb_ctrl_dma_addr, &reg->out_endp[EP0_CON].doepdma);
+       writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), 
&reg->out_endp[EP0_CON].doepdma);
 
        ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
        writel(ep_ctrl|DEPCTL_EPENA, &reg->out_endp[EP0_CON].doepctl);
@@ -75,7 +75,7 @@ static inline void dwc2_ep0_complete_out(void)
 
        writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
               &reg->out_endp[EP0_CON].doeptsiz);
-       writel(usb_ctrl_dma_addr, &reg->out_endp[EP0_CON].doepdma);
+       writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), 
&reg->out_endp[EP0_CON].doepdma);
 
        ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
        writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
@@ -113,7 +113,7 @@ static int setdma_rx(struct dwc2_ep *ep, struct 
dwc2_request *req)
                                (unsigned long) ep->dma_buf +
                                ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
 
-       writel((unsigned long) ep->dma_buf, &reg->out_endp[ep_num].doepdma);
+       writel(phys_to_bus((unsigned long)ep->dma_buf), 
&reg->out_endp[ep_num].doepdma);
        writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
               &reg->out_endp[ep_num].doeptsiz);
        writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->out_endp[ep_num].doepctl);
@@ -161,7 +161,7 @@ static int setdma_tx(struct dwc2_ep *ep, struct 
dwc2_request *req)
        while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
                ;
 
-       writel((unsigned long) ep->dma_buf, &reg->in_endp[ep_num].diepdma);
+       writel(phys_to_bus((unsigned long)ep->dma_buf), 
&reg->in_endp[ep_num].diepdma);
        writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
               &reg->in_endp[ep_num].dieptsiz);
 
@@ -921,7 +921,7 @@ static int dwc2_udc_get_status(struct dwc2_udc *dev,
                           (unsigned long) usb_ctrl +
                           ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE));
 
-       writel(usb_ctrl_dma_addr, &reg->in_endp[EP0_CON].diepdma);
+       writel(phys_to_bus(usb_ctrl_dma_addr), &reg->in_endp[EP0_CON].diepdma);
        writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
               &reg->in_endp[EP0_CON].dieptsiz);
 
-- 
2.17.1

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