On Wed, Oct 2, 2019 at 5:20 PM Simon Goldschmidt
<simon.k.r.goldschm...@gmail.com> wrote:
>
> On Tue, Sep 10, 2019 at 10:38 AM Ley Foon Tan <ley.foon....@intel.com> wrote:
> >
> > Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
> > to defines.
> > No functional change.
> >
> > Signed-off-by: Ley Foon Tan <ley.foon....@intel.com>
> >
> > ---
> > v2:
> > - Change to use writel(), readl() and etc.
> > - Get base address from DT.
>
> Same as 2/4: separate patch please.
Same for this, will remove "no functional change" in commit message.
Thanks
Ley Foon
>
> > - Add prefix to defines.
> > ---
> > arch/arm/mach-socfpga/clock_manager_s10.c | 4 +-
> > .../include/mach/system_manager.h | 2 +
> > .../include/mach/system_manager_arria10.h | 94 +++------
> > .../include/mach/system_manager_gen5.h | 123 +++---------
> > .../include/mach/system_manager_s10.h | 184 +++++++-----------
> > arch/arm/mach-socfpga/mailbox_s10.c | 6 +-
> > arch/arm/mach-socfpga/misc.c | 5 +
> > arch/arm/mach-socfpga/misc_arria10.c | 9 +-
> > arch/arm/mach-socfpga/misc_gen5.c | 22 ++-
> > arch/arm/mach-socfpga/misc_s10.c | 9 +-
> > arch/arm/mach-socfpga/reset_manager_arria10.c | 24 +--
> > arch/arm/mach-socfpga/reset_manager_gen5.c | 7 +-
> > arch/arm/mach-socfpga/reset_manager_s10.c | 18 +-
> > arch/arm/mach-socfpga/scan_manager.c | 6 +-
> > arch/arm/mach-socfpga/spl_a10.c | 5 +-
> > arch/arm/mach-socfpga/spl_gen5.c | 11 +-
> > arch/arm/mach-socfpga/spl_s10.c | 12 +-
> > arch/arm/mach-socfpga/system_manager_gen5.c | 38 ++--
> > arch/arm/mach-socfpga/system_manager_s10.c | 39 ++--
> > arch/arm/mach-socfpga/wrap_pll_config_s10.c | 11 +-
> > drivers/ddr/altera/sdram_gen5.c | 10 +-
> > drivers/ddr/altera/sdram_s10.c | 6 +-
> > drivers/fpga/socfpga_arria10.c | 7 +-
> > drivers/fpga/socfpga_gen5.c | 4 +-
> > drivers/mmc/socfpga_dw_mmc.c | 6 +-
> > 25 files changed, 240 insertions(+), 422 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c
> > b/arch/arm/mach-socfpga/clock_manager_s10.c
> > index 3ba2a00c02..6cbf07ac6f 100644
> > --- a/arch/arm/mach-socfpga/clock_manager_s10.c
> > +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> > @@ -14,8 +14,6 @@ DECLARE_GLOBAL_DATA_PTR;
> >
> > static const struct socfpga_clock_manager *clock_manager_base =
> > (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> > -static const struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> >
> > /*
> > * function to write the bypass register which requires a poll of the
> > @@ -351,7 +349,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> >
> > unsigned int cm_get_qspi_controller_clk_hz(void)
> > {
> > - return readl(&sysmgr_regs->boot_scratch_cold0);
> > + return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD0);
> > }
> >
> > unsigned int cm_get_spi_controller_clk_hz(void)
> > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h
> > b/arch/arm/mach-socfpga/include/mach/system_manager.h
> > index 7e76df74b7..803305eb35 100644
> > --- a/arch/arm/mach-socfpga/include/mach/system_manager.h
> > +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
> > @@ -6,6 +6,8 @@
> > #ifndef _SYSTEM_MANAGER_H_
> > #define _SYSTEM_MANAGER_H_
> >
> > +extern phys_addr_t socfpga_sysmgr_base;
> > +
> > #if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> > #include <asm/arch/system_manager_s10.h>
> > #else
> > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> > b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> > index 14052b957c..1a45c0f134 100644
> > --- a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> > @@ -6,73 +6,33 @@
> > #ifndef _SYSTEM_MANAGER_ARRIA10_H_
> > #define _SYSTEM_MANAGER_ARRIA10_H_
> >
> > -struct socfpga_system_manager {
> > - u32 siliconid1;
> > - u32 siliconid2;
> > - u32 wddbg;
> > - u32 bootinfo;
> > - u32 mpu_ctrl_l2_ecc;
> > - u32 _pad_0x14_0x1f[3];
> > - u32 dma;
> > - u32 dma_periph;
> > - u32 sdmmcgrp_ctrl;
> > - u32 sdmmc_l3master;
> > - u32 nand_bootstrap;
> > - u32 nand_l3master;
> > - u32 usb0_l3master;
> > - u32 usb1_l3master;
> > - u32 emac_global;
> > - u32 emac[3];
> > - u32 _pad_0x50_0x5f[4];
> > - u32 fpgaintf_en_global;
> > - u32 fpgaintf_en_0;
> > - u32 fpgaintf_en_1;
> > - u32 fpgaintf_en_2;
> > - u32 fpgaintf_en_3;
> > - u32 _pad_0x74_0x7f[3];
> > - u32 noc_addr_remap_value;
> > - u32 noc_addr_remap_set;
> > - u32 noc_addr_remap_clear;
> > - u32 _pad_0x8c_0x8f;
> > - u32 ecc_intmask_value;
> > - u32 ecc_intmask_set;
> > - u32 ecc_intmask_clr;
> > - u32 ecc_intstatus_serr;
> > - u32 ecc_intstatus_derr;
> > - u32 mpu_status_l2_ecc;
> > - u32 mpu_clear_l2_ecc;
> > - u32 mpu_status_l1_parity;
> > - u32 mpu_clear_l1_parity;
> > - u32 mpu_set_l1_parity;
> > - u32 _pad_0xb8_0xbf[2];
> > - u32 noc_timeout;
> > - u32 noc_idlereq_set;
> > - u32 noc_idlereq_clr;
> > - u32 noc_idlereq_value;
> > - u32 noc_idleack;
> > - u32 noc_idlestatus;
> > - u32 fpga2soc_ctrl;
> > - u32 _pad_0xdc_0xff[9];
> > - u32 tsmc_tsel_0;
> > - u32 tsmc_tsel_1;
> > - u32 tsmc_tsel_2;
> > - u32 tsmc_tsel_3;
> > - u32 _pad_0x110_0x200[60];
> > - u32 romhw_ctrl;
> > - u32 romcode_ctrl;
> > - u32 romcode_cpu1startaddr;
> > - u32 romcode_initswstate;
> > - u32 romcode_initswlastld;
> > - u32 _pad_0x214_0x217;
> > - u32 warmram_enable;
> > - u32 warmram_datastart;
> > - u32 warmram_length;
> > - u32 warmram_execution;
> > - u32 warmram_crc;
> > - u32 _pad_0x22c_0x22f;
> > - u32 isw_handoff[8];
> > - u32 romcode_bootromswstate[8];
> > -};
> > +#define SYSMGR_A10_WDDBG 0x8
> > +#define SYSMGR_A10_BOOTINFO 0xc
> > +#define SYSMGR_A10_DMA 0x20
> > +#define SYSMGR_A10_DMA_PERIPH 0x24
> > +#define SYSMGR_A10_SDMMC 0x28
> > +#define SYSMGR_A10_SDMMC_L3MASTER 0x2c
> > +#define SYSMGR_A10_EMAC_GLOBAL 0x40
> > +#define SYSMGR_A10_EMAC0 0x44
> > +#define SYSMGR_A10_EMAC1 0x48
> > +#define SYSMGR_A10_EMAC2 0x4c
> > +#define SYSMGR_A10_FPGAINTF_EN_GLOBAL 0x60
> > +#define SYSMGR_A10_FPGAINTF_EN0 0x64
> > +#define SYSMGR_A10_FPGAINTF_EN1 0x68
> > +#define SYSMGR_A10_FPGAINTF_EN2 0x6c
> > +#define SYSMGR_A10_FPGAINTF_EN3 0x70
> > +#define SYSMGR_A10_ECC_INTMASK_VAL 0x90
> > +#define SYSMGR_A10_ECC_INTMASK_SET 0x94
> > +#define SYSMGR_A10_ECC_INTMASK_CLR 0x98
> > +#define SYSMGR_A10_NOC_TIMEOUT 0xc0
> > +#define SYSMGR_A10_NOC_IDLEREQ_SET 0xc4
> > +#define SYSMGR_A10_NOC_IDLEREQ_CLR 0xc8
> > +#define SYSMGR_A10_NOC_IDLEREQ_VAL 0xcc
> > +#define SYSMGR_A10_NOC_IDLEACK 0xd0
> > +#define SYSMGR_A10_NOC_IDLESTATUS 0xd4
> > +#define SYSMGR_A10_FPGA2SOC_CTRL 0xd8
> > +
> > +#define SYSMGR_SDMMC SYSMGR_A10_SDMMC
> >
> > #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
> > #define SYSMGR_BOOTINFO_BSEL_SHIFT 12
> > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
> > b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
> > index 52e59df513..90cb465d13 100644
> > --- a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
> > +++ b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
> > @@ -13,106 +13,29 @@ void sysmgr_config_warmrstcfgio(int enable);
> >
> > void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
> >
> > -struct socfpga_system_manager {
> > - /* System Manager Module */
> > - u32 siliconid1; /* 0x00 */
> > - u32 siliconid2;
> > - u32 _pad_0x8_0xf[2];
> > - u32 wddbg; /* 0x10 */
> > - u32 bootinfo;
> > - u32 hpsinfo;
> > - u32 parityinj;
> > - /* FPGA Interface Group */
> > - u32 fpgaintfgrp_gbl; /* 0x20 */
> > - u32 fpgaintfgrp_indiv;
> > - u32 fpgaintfgrp_module;
> > - u32 _pad_0x2c_0x2f;
> > - /* Scan Manager Group */
> > - u32 scanmgrgrp_ctrl; /* 0x30 */
> > - u32 _pad_0x34_0x3f[3];
> > - /* Freeze Control Group */
> > - u32 frzctrl_vioctrl; /* 0x40 */
> > - u32 _pad_0x44_0x4f[3];
> > - u32 frzctrl_hioctrl; /* 0x50 */
> > - u32 frzctrl_src;
> > - u32 frzctrl_hwctrl;
> > - u32 _pad_0x5c_0x5f;
> > - /* EMAC Group */
> > - u32 emacgrp_ctrl; /* 0x60 */
> > - u32 emacgrp_l3master;
> > - u32 _pad_0x68_0x6f[2];
> > - /* DMA Controller Group */
> > - u32 dmagrp_ctrl; /* 0x70 */
> > - u32 dmagrp_persecurity;
> > - u32 _pad_0x78_0x7f[2];
> > - /* Preloader (initial software) Group */
> > - u32 iswgrp_handoff[8]; /* 0x80 */
> > - u32 _pad_0xa0_0xbf[8]; /* 0xa0 */
> > - /* Boot ROM Code Register Group */
> > - u32 romcodegrp_ctrl; /* 0xc0 */
> > - u32 romcodegrp_cpu1startaddr;
> > - u32 romcodegrp_initswstate;
> > - u32 romcodegrp_initswlastld;
> > - u32 romcodegrp_bootromswstate; /* 0xd0 */
> > - u32 __pad_0xd4_0xdf[3];
> > - /* Warm Boot from On-Chip RAM Group */
> > - u32 romcodegrp_warmramgrp_enable; /* 0xe0 */
> > - u32 romcodegrp_warmramgrp_datastart;
> > - u32 romcodegrp_warmramgrp_length;
> > - u32 romcodegrp_warmramgrp_execution;
> > - u32 romcodegrp_warmramgrp_crc; /* 0xf0 */
> > - u32 __pad_0xf4_0xff[3];
> > - /* Boot ROM Hardware Register Group */
> > - u32 romhwgrp_ctrl; /* 0x100 */
> > - u32 _pad_0x104_0x107;
> > - /* SDMMC Controller Group */
> > - u32 sdmmcgrp_ctrl;
> > - u32 sdmmcgrp_l3master;
> > - /* NAND Flash Controller Register Group */
> > - u32 nandgrp_bootstrap; /* 0x110 */
> > - u32 nandgrp_l3master;
> > - /* USB Controller Group */
> > - u32 usbgrp_l3master;
> > - u32 _pad_0x11c_0x13f[9];
> > - /* ECC Management Register Group */
> > - u32 eccgrp_l2; /* 0x140 */
> > - u32 eccgrp_ocram;
> > - u32 eccgrp_usb0;
> > - u32 eccgrp_usb1;
> > - u32 eccgrp_emac0; /* 0x150 */
> > - u32 eccgrp_emac1;
> > - u32 eccgrp_dma;
> > - u32 eccgrp_can0;
> > - u32 eccgrp_can1; /* 0x160 */
> > - u32 eccgrp_nand;
> > - u32 eccgrp_qspi;
> > - u32 eccgrp_sdmmc;
> > - u32 _pad_0x170_0x3ff[164];
> > - /* Pin Mux Control Group */
> > - u32 emacio[20]; /* 0x400 */
> > - u32 flashio[12]; /* 0x450 */
> > - u32 generalio[28]; /* 0x480 */
> > - u32 _pad_0x4f0_0x4ff[4];
> > - u32 mixed1io[22]; /* 0x500 */
> > - u32 mixed2io[8]; /* 0x558 */
> > - u32 gplinmux[23]; /* 0x578 */
> > - u32 gplmux[71]; /* 0x5d4 */
> > - u32 nandusefpga; /* 0x6f0 */
> > - u32 _pad_0x6f4;
> > - u32 rgmii1usefpga; /* 0x6f8 */
> > - u32 _pad_0x6fc_0x700[2];
> > - u32 i2c0usefpga; /* 0x704 */
> > - u32 sdmmcusefpga; /* 0x708 */
> > - u32 _pad_0x70c_0x710[2];
> > - u32 rgmii0usefpga; /* 0x714 */
> > - u32 _pad_0x718_0x720[3];
> > - u32 i2c3usefpga; /* 0x724 */
> > - u32 i2c2usefpga; /* 0x728 */
> > - u32 i2c1usefpga; /* 0x72c */
> > - u32 spim1usefpga; /* 0x730 */
> > - u32 _pad_0x734;
> > - u32 spim0usefpga; /* 0x738 */
> > -};
> > +#define SYSMGR_GEN5_WDDBG 0x10
> > +#define SYSMGR_GEN5_BOOTINFO 0x14
> > +#define SYSMGR_GEN5_FPGAINFGRP_GBL 0x20
> > +#define SYSMGR_GEN5_FPGAINFGRP_INDIV 0x24
> > +#define SYSMGR_GEN5_FPGAINFGRP_MODULE 0x28
> > +#define SYSMGR_GEN5_SCANMGRGRP_CTRL 0x30
> > +#define SYSMGR_GEN5_ISWGRP_HANDOFF 0x80
> > +#define SYSMGR_GEN5_ROMCODEGRP_CTRL 0xc0
> > +#define SYSMGR_GEN5_WARMRAMGRP_EN 0xe0
> > +#define SYSMGR_GEN5_SDMMC 0x108
> > +#define SYSMGR_GEN5_ECCGRP_OCRAM 0x144
> > +#define SYSMGR_GEN5_EMACIO 0x400
> > +#define SYSMGR_GEN5_NAND_USEFPGA 0x6f0
> > +#define SYSMGR_GEN5_RGMII0_USEFPGA 0x6f8
> > +#define SYSMGR_GEN5_SDMMC_USEFPGA 0x708
> > +#define SYSMGR_GEN5_RGMII1_USEFPGA 0x704
> > +#define SYSMGR_GEN5_SPIM1_USEFPGA 0x730
> > +#define SYSMGR_GEN5_SPIM0_USEFPGA 0x738
> > +
> > +#define SYSMGR_SDMMC SYSMGR_GEN5_SDMMC
> > +
> > +#define SYSMGR_ISWGRP_HANDOFF_OFFSET(i) \
> > + SYSMGR_GEN5_ISWGRP_HANDOFF + ((i) * sizeof(u32))
> > #endif
> >
> > #define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
> > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
> > b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
> > index 297f9e1999..e68a8e730e 100644
> > --- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
> > @@ -15,125 +15,73 @@ void sysmgr_pinmux_table_ctrl(const u32 **table,
> > unsigned int *table_len);
> > void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
> > void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
> >
> > -struct socfpga_system_manager {
> > - /* System Manager Module */
> > - u32 siliconid1; /* 0x00 */
> > - u32 siliconid2;
> > - u32 wddbg;
> > - u32 _pad_0xc;
> > - u32 mpu_status; /* 0x10 */
> > - u32 mpu_ace;
> > - u32 _pad_0x18_0x1c[2];
> > - u32 dma; /* 0x20 */
> > - u32 dma_periph;
> > - /* SDMMC Controller Group */
> > - u32 sdmmcgrp_ctrl;
> > - u32 sdmmcgrp_l3master;
> > - /* NAND Flash Controller Register Group */
> > - u32 nandgrp_bootstrap; /* 0x30 */
> > - u32 nandgrp_l3master;
> > - /* USB Controller Group */
> > - u32 usb0_l3master;
> > - u32 usb1_l3master;
> > - /* EMAC Group */
> > - u32 emac_gbl; /* 0x40 */
> > - u32 emac0;
> > - u32 emac1;
> > - u32 emac2;
> > - u32 emac0_ace; /* 0x50 */
> > - u32 emac1_ace;
> > - u32 emac2_ace;
> > - u32 nand_axuser;
> > - u32 _pad_0x60_0x64[2]; /* 0x60 */
> > - /* FPGA interface Group */
> > - u32 fpgaintf_en_1;
> > - u32 fpgaintf_en_2;
> > - u32 fpgaintf_en_3; /* 0x70 */
> > - u32 dma_l3master;
> > - u32 etr_l3master;
> > - u32 _pad_0x7c;
> > - u32 sec_ctrl_slt; /* 0x80 */
> > - u32 osc_trim;
> > - u32 _pad_0x88_0x8c[2];
> > - /* ECC Group */
> > - u32 ecc_intmask_value; /* 0x90 */
> > - u32 ecc_intmask_set;
> > - u32 ecc_intmask_clr;
> > - u32 ecc_intstatus_serr;
> > - u32 ecc_intstatus_derr; /* 0xa0 */
> > - u32 _pad_0xa4_0xac[3];
> > - u32 noc_addr_remap; /* 0xb0 */
> > - u32 hmc_clk;
> > - u32 io_pa_ctrl;
> > - u32 _pad_0xbc;
> > - /* NOC Group */
> > - u32 noc_timeout; /* 0xc0 */
> > - u32 noc_idlereq_set;
> > - u32 noc_idlereq_clr;
> > - u32 noc_idlereq_value;
> > - u32 noc_idleack; /* 0xd0 */
> > - u32 noc_idlestatus;
> > - u32 fpga2soc_ctrl;
> > - u32 fpga_config;
> > - u32 iocsrclk_gate; /* 0xe0 */
> > - u32 gpo;
> > - u32 gpi;
> > - u32 _pad_0xec;
> > - u32 mpu; /* 0xf0 */
> > - u32 sdm_hps_spare;
> > - u32 hps_sdm_spare;
> > - u32 _pad_0xfc_0x1fc[65];
> > - /* Boot scratch register group */
> > - u32 boot_scratch_cold0; /* 0x200 */
> > - u32 boot_scratch_cold1;
> > - u32 boot_scratch_cold2;
> > - u32 boot_scratch_cold3;
> > - u32 boot_scratch_cold4; /* 0x210 */
> > - u32 boot_scratch_cold5;
> > - u32 boot_scratch_cold6;
> > - u32 boot_scratch_cold7;
> > - u32 boot_scratch_cold8; /* 0x220 */
> > - u32 boot_scratch_cold9;
> > - u32 _pad_0x228_0xffc[886];
> > - /* Pin select and pin control group */
> > - u32 pinsel0[40]; /* 0x1000 */
> > - u32 _pad_0x10a0_0x10fc[24];
> > - u32 pinsel40[8];
> > - u32 _pad_0x1120_0x112c[4];
> > - u32 ioctrl0[28];
> > - u32 _pad_0x11a0_0x11fc[24];
> > - u32 ioctrl28[20];
> > - u32 _pad_0x1250_0x12fc[44];
> > - /* Use FPGA mux */
> > - u32 rgmii0usefpga; /* 0x1300 */
> > - u32 rgmii1usefpga;
> > - u32 rgmii2usefpga;
> > - u32 i2c0usefpga;
> > - u32 i2c1usefpga;
> > - u32 i2c_emac0_usefpga;
> > - u32 i2c_emac1_usefpga;
> > - u32 i2c_emac2_usefpga;
> > - u32 nandusefpga;
> > - u32 _pad_0x1324;
> > - u32 spim0usefpga;
> > - u32 spim1usefpga;
> > - u32 spis0usefpga;
> > - u32 spis1usefpga;
> > - u32 uart0usefpga;
> > - u32 uart1usefpga;
> > - u32 mdio0usefpga;
> > - u32 mdio1usefpga;
> > - u32 mdio2usefpga;
> > - u32 _pad_0x134c;
> > - u32 jtagusefpga;
> > - u32 sdmmcusefpga;
> > - u32 hps_osc_clk;
> > - u32 _pad_0x135c_0x13fc[41];
> > - u32 iodelay0[40];
> > - u32 _pad_0x14a0_0x14fc[24];
> > - u32 iodelay40[8];
> > +#define SYSMGR_S10_WDDBG 0x8
> > +#define SYSMGR_S10_DMA 0x20
> > +#define SYSMGR_S10_DMA_PERIPH 0x24
> > +#define SYSMGR_S10_SDMMC 0x28
> > +#define SYSMGR_S10_SDMMC_L3MASTER 0x2c
> > +#define SYSMGR_S10_EMAC_GLOBAL 0x40
> > +#define SYSMGR_S10_EMAC0 0x44
> > +#define SYSMGR_S10_EMAC1 0x48
> > +#define SYSMGR_S10_EMAC2 0x4c
> > +#define SYSMGR_S10_EMAC0_ACE 0x50
> > +#define SYSMGR_S10_EMAC1_ACE 0x54
> > +#define SYSMGR_S10_EMAC2_ACE 0x58
> > +#define SYSMGR_S10_NAND_AXUSER 0x5c
> > +#define SYSMGR_S10_FPGAINTF_EN1 0x68
> > +#define SYSMGR_S10_FPGAINTF_EN2 0x6c
> > +#define SYSMGR_S10_FPGAINTF_EN3 0x70
> > +#define SYSMGR_S10_DMA_L3MASTER 0x74
> > +#define SYSMGR_S10_HMC_CLK 0xb4
> > +#define SYSMGR_S10_IO_PA_CTRL 0xb8
> > +#define SYSMGR_S10_NOC_TIMEOUT 0xc0
> > +#define SYSMGR_S10_NOC_IDLEREQ_SET 0xc4
> > +#define SYSMGR_S10_NOC_IDLEREQ_CLR 0xc8
> > +#define SYSMGR_S10_NOC_IDLEREQ_VAL 0xcc
> > +#define SYSMGR_S10_NOC_IDLEACK 0xd0
> > +#define SYSMGR_S10_NOC_IDLESTATUS 0xd4
> > +#define SYSMGR_S10_FPGA2SOC_CTRL 0xd8
> > +#define SYSMGR_S10_FPGA_CONFIG 0xdc
> > +#define SYSMGR_S10_IOCSRCLK_GATE 0xe0
> > +#define SYSMGR_S10_GPO 0xe4
> > +#define SYSMGR_S10_GPI 0xe8
> > +#define SYSMGR_S10_MPU 0xf0
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD0 0x200
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD1 0x204
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD2 0x208
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD3 0x20c
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD4 0x210
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD5 0x214
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD6 0x218
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD7 0x21c
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD8 0x220
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD9 0x224
> > +#define SYSMGR_S10_PINSEL0 0x1000
> > +#define SYSMGR_S10_IOCTRL0 0x1130
> > +#define SYSMGR_S10_EMAC0_USEFPGA 0x1300
> > +#define SYSMGR_S10_EMAC1_USEFPGA 0x1304
> > +#define SYSMGR_S10_EMAC2_USEFPGA 0x1308
> > +#define SYSMGR_S10_I2C0_USEFPGA 0x130c
> > +#define SYSMGR_S10_I2C1_USEFPGA 0x1310
> > +#define SYSMGR_S10_I2C_EMAC0_USEFPGA 0x1314
> > +#define SYSMGR_S10_I2C_EMAC1_USEFPGA 0x1318
> > +#define SYSMGR_S10_I2C_EMAC2_USEFPGA 0x131c
> > +#define SYSMGR_S10_NAND_USEFPGA 0x1320
> > +#define SYSMGR_S10_SPIM0_USEFPGA 0x1328
> > +#define SYSMGR_S10_SPIM1_USEFPGA 0x132c
> > +#define SYSMGR_S10_SPIS0_USEFPGA 0x1330
> > +#define SYSMGR_S10_SPIS1_USEFPGA 0x1334
> > +#define SYSMGR_S10_UART0_USEFPGA 0x1338
> > +#define SYSMGR_S10_UART1_USEFPGA 0x133c
> > +#define SYSMGR_S10_MDIO0_USEFPGA 0x1340
> > +#define SYSMGR_S10_MDIO1_USEFPGA 0x1344
> > +#define SYSMGR_S10_MDIO2_USEFPGA 0x1348
> > +#define SYSMGR_S10_JTAG_USEFPGA 0x1350
> > +#define SYSMGR_S10_SDMMC_USEFPGA 0x1354
> > +#define SYSMGR_S10_HPS_OSC_CLK 0x1358
> > +#define SYSMGR_S10_IODELAY0 0x1400
> >
> > -};
> > +#define SYSMGR_SDMMC SYSMGR_S10_SDMMC
> >
> > #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
> > #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
> > diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
> > b/arch/arm/mach-socfpga/mailbox_s10.c
> > index 4498ab55df..11b57361c7 100644
> > --- a/arch/arm/mach-socfpga/mailbox_s10.c
> > +++ b/arch/arm/mach-socfpga/mailbox_s10.c
> > @@ -287,9 +287,6 @@ int mbox_qspi_close(void)
> >
> > int mbox_qspi_open(void)
> > {
> > - static const struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > int ret;
> > u32 resp_buf[1];
> > u32 resp_buf_len;
> > @@ -318,7 +315,8 @@ int mbox_qspi_open(void)
> >
> > /* We are getting QSPI ref clock and set into sysmgr boot register
> > */
> > printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
> > - writel(resp_buf[0], &sysmgr_regs->boot_scratch_cold0);
> > + writel(resp_buf[0],
> > + socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD0);
> >
> > return 0;
> >
> > diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> > index 901c432f82..fcc53b6fbc 100644
> > --- a/arch/arm/mach-socfpga/misc.c
> > +++ b/arch/arm/mach-socfpga/misc.c
> > @@ -23,6 +23,7 @@
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > phys_addr_t socfpga_rstmgr_base __section(".data");
> > +phys_addr_t socfpga_sysmgr_base __section(".data");
> >
> > #ifdef CONFIG_SYS_L2_PL310
> > static const struct pl310_regs *const pl310 =
> > @@ -233,4 +234,8 @@ void socfpga_get_manager_addr(void)
> > socfpga_rstmgr_base = socfpga_get_base_addr("altr,rst-mgr");
> > if (!socfpga_rstmgr_base)
> > hang();
> > +
> > + socfpga_sysmgr_base = socfpga_get_base_addr("altr,sys-mgr");
> > + if (!socfpga_sysmgr_base)
> > + hang();
> > }
> > diff --git a/arch/arm/mach-socfpga/misc_arria10.c
> > b/arch/arm/mach-socfpga/misc_arria10.c
> > index 2e2a40b65d..ff6ab83441 100644
> > --- a/arch/arm/mach-socfpga/misc_arria10.c
> > +++ b/arch/arm/mach-socfpga/misc_arria10.c
> > @@ -28,9 +28,6 @@
> > #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
> > #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
> >
> > -static struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > /*
> > * FPGA programming support for SoC FPGA Arria 10
> > */
> > @@ -81,7 +78,7 @@ void socfpga_init_security_policies(void)
> > writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST);
> > writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4);
> >
> > - writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set);
> > + writel(0x0007FFFF, socfpga_sysmgr_base +
> > SYSMGR_A10_ECC_INTMASK_SET);
> > }
> >
> > void socfpga_sdram_remap_zero(void)
> > @@ -105,8 +102,8 @@ int arch_early_init_r(void)
> > #if defined(CONFIG_DISPLAY_CPUINFO)
> > int print_cpuinfo(void)
> > {
> > - const u32 bsel =
> > - SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
> > + u32 bootinfo = readl(socfpga_sysmgr_base + SYSMGR_A10_BOOTINFO);
> > + const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
> >
> > puts("CPU: Altera SoCFPGA Arria 10\n");
> >
> > diff --git a/arch/arm/mach-socfpga/misc_gen5.c
> > b/arch/arm/mach-socfpga/misc_gen5.c
> > index b39a66562d..7735958e9c 100644
> > --- a/arch/arm/mach-socfpga/misc_gen5.c
> > +++ b/arch/arm/mach-socfpga/misc_gen5.c
> > @@ -28,8 +28,6 @@ DECLARE_GLOBAL_DATA_PTR;
> >
> > static struct pl310_regs *const pl310 =
> > (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> > -static struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > static struct nic301_registers *nic301_regs =
> > (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> > static struct scu_registers *scu_regs =
> > @@ -118,8 +116,8 @@ static int socfpga_fpga_id(const bool print_id)
> > #if defined(CONFIG_DISPLAY_CPUINFO)
> > int print_cpuinfo(void)
> > {
> > - const u32 bsel =
> > - SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
> > + u32 bootinfo = readl(socfpga_sysmgr_base + SYSMGR_GEN5_BOOTINFO);
> > + const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
> >
> > puts("CPU: Altera SoCFPGA Platform\n");
> > socfpga_fpga_id(1);
> > @@ -132,7 +130,8 @@ int print_cpuinfo(void)
> > #ifdef CONFIG_ARCH_MISC_INIT
> > int arch_misc_init(void)
> > {
> > - const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
> > + const u32 bsel = readl(socfpga_sysmgr_base +
> > + SYSMGR_GEN5_BOOTINFO) & 0x7;
> > const int fpga_id = socfpga_fpga_id(0);
> > env_set("bootmode", bsel_str[bsel].mode);
> > if (fpga_id >= 0)
> > @@ -190,10 +189,11 @@ int arch_early_init_r(void)
> > * to support that old code, we write it here instead of in the
> > * reset_cpu() function just before resetting the CPU.
> > */
> > - writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
> > + writel(0xae9efebc, socfpga_sysmgr_base + SYSMGR_GEN5_WARMRAMGRP_EN);
> >
> > for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
> > - iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
> > + iswgrp_handoff[i] = readl(socfpga_sysmgr_base +
> > + SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
> >
> > socfpga_bridges_reset(1);
> >
> > @@ -219,16 +219,18 @@ void do_bridge_reset(int enable, unsigned int mask)
> > !(mask & BIT(2)));
> > for (i = 0; i < 2; i++) { /* Reload SW setting cache
> > */
> > iswgrp_handoff[i] =
> > - readl(&sysmgr_regs->iswgrp_handoff[i]);
> > + readl(socfpga_sysmgr_base +
> > + SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
> > }
> >
> > - writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
> > + writel(iswgrp_handoff[2],
> > + socfpga_sysmgr_base + SYSMGR_GEN5_FPGAINFGRP_MODULE);
> > writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
> > writel(iswgrp_handoff[0],
> > socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
> > writel(iswgrp_handoff[1], &nic301_regs->remap);
> > } else {
> > - writel(0, &sysmgr_regs->fpgaintfgrp_module);
> > + writel(0, socfpga_sysmgr_base +
> > SYSMGR_GEN5_FPGAINFGRP_MODULE);
> > writel(0, &sdr_ctrl->fpgaport_rst);
> > writel(0, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
> > writel(1, &nic301_regs->remap);
> > diff --git a/arch/arm/mach-socfpga/misc_s10.c
> > b/arch/arm/mach-socfpga/misc_s10.c
> > index 0a5fab11c0..16fbf71599 100644
> > --- a/arch/arm/mach-socfpga/misc_s10.c
> > +++ b/arch/arm/mach-socfpga/misc_s10.c
> > @@ -23,9 +23,6 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > /*
> > * FPGA programming support for SoC FPGA Stratix 10
> > */
> > @@ -68,9 +65,9 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const
> > char *phymode)
> > else
> > return -EINVAL;
> >
> > - clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index,
> > - SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
> > - modereg);
> > + clrsetbits_le32((unsigned long)(socfpga_sysmgr_base +
> > SYSMGR_S10_EMAC0 +
> > + gmac_index),
> > + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
> >
> > return 0;
> > }
> > diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c
> > b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > index 4553653992..5611e784e6 100644
> > --- a/arch/arm/mach-socfpga/reset_manager_arria10.c
> > +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > @@ -15,9 +15,6 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static const struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > struct bridge_cfg {
> > int compat_id;
> > u32 mask_noc;
> > @@ -98,14 +95,16 @@ int socfpga_reset_deassert_bridges_handoff(void)
> > }
> >
> > /* clear idle request to all bridges */
> > - setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
> > + setbits_le32(socfpga_sysmgr_base + SYSMGR_A10_NOC_IDLEREQ_CLR,
> > + mask_noc);
> >
> > /* Release bridges from reset state per handoff value */
> > clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST,
> > mask_rstmgr);
> >
> > /* Poll until all idleack to 0, timeout at 1000ms */
> > - return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
> > - false, 1000, false);
> > + return wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
> > + SYSMGR_A10_NOC_IDLEACK),
> > + mask_noc, false, 1000, false);
> > }
> >
> > /* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
> > @@ -195,13 +194,15 @@ int socfpga_bridges_reset(void)
> > ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
> > ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
> > ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
> > - &sysmgr_regs->noc_idlereq_set);
> > + socfpga_sysmgr_base + SYSMGR_A10_NOC_IDLEREQ_SET);
> >
> > /* Enable the NOC timeout */
> > - writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout);
> > + writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK,
> > + socfpga_sysmgr_base + SYSMGR_A10_NOC_TIMEOUT);
> >
> > /* Poll until all idleack to 1 */
> > - ret = wait_for_bit_le32(&sysmgr_regs->noc_idleack,
> > + ret = wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
> > + SYSMGR_A10_NOC_IDLEACK),
> > ALT_SYSMGR_NOC_H2F_SET_MSK |
> > ALT_SYSMGR_NOC_LWH2F_SET_MSK |
> > ALT_SYSMGR_NOC_F2H_SET_MSK |
> > @@ -213,7 +214,8 @@ int socfpga_bridges_reset(void)
> > return ret;
> >
> > /* Poll until all idlestatus to 1 */
> > - ret = wait_for_bit_le32(&sysmgr_regs->noc_idlestatus,
> > + ret = wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
> > + SYSMGR_A10_NOC_IDLESTATUS),
> > ALT_SYSMGR_NOC_H2F_SET_MSK |
> > ALT_SYSMGR_NOC_LWH2F_SET_MSK |
> > ALT_SYSMGR_NOC_F2H_SET_MSK |
> > @@ -234,7 +236,7 @@ int socfpga_bridges_reset(void)
> > ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
> >
> > /* Disable NOC timeout */
> > - writel(0, &sysmgr_regs->noc_timeout);
> > + writel(0, socfpga_sysmgr_base + SYSMGR_A10_NOC_TIMEOUT);
> >
> > return 0;
> > }
> > diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c
> > b/arch/arm/mach-socfpga/reset_manager_gen5.c
> > index ad31214711..6b617fd016 100644
> > --- a/arch/arm/mach-socfpga/reset_manager_gen5.c
> > +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
> > @@ -10,9 +10,6 @@
> > #include <asm/arch/reset_manager.h>
> > #include <asm/arch/system_manager.h>
> >
> > -static const struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > /* Assert or de-assert SoCFPGA reset manager reset. */
> > void socfpga_per_reset(u32 reset, int set)
> > {
> > @@ -83,8 +80,8 @@ void socfpga_bridges_set_handoff_regs(bool h2f, bool
> > lwh2f, bool f2h)
> > if (f2h)
> > brgmask |= BIT(2);
> >
> > - writel(brgmask, &sysmgr_regs->iswgrp_handoff[0]);
> > - writel(l3rmask, &sysmgr_regs->iswgrp_handoff[1]);
> > + writel(brgmask, socfpga_sysmgr_base +
> > SYSMGR_ISWGRP_HANDOFF_OFFSET(0));
> > + writel(l3rmask, socfpga_sysmgr_base +
> > SYSMGR_ISWGRP_HANDOFF_OFFSET(1));
> > }
> >
> > void socfpga_bridges_reset(int enable)
> > diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
> > b/arch/arm/mach-socfpga/reset_manager_s10.c
> > index b196d58d3d..50a2d80930 100644
> > --- a/arch/arm/mach-socfpga/reset_manager_s10.c
> > +++ b/arch/arm/mach-socfpga/reset_manager_s10.c
> > @@ -12,9 +12,6 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static const struct socfpga_system_manager *system_manager_base =
> > - (void *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > /* Assert or de-assert SoCFPGA reset manager reset. */
> > void socfpga_per_reset(u32 reset, int set)
> > {
> > @@ -59,28 +56,29 @@ void socfpga_bridges_reset(int enable)
> > {
> > if (enable) {
> > /* clear idle request to all bridges */
> > - setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
> > + setbits_le32(socfpga_sysmgr_base +
> > SYSMGR_S10_NOC_IDLEREQ_CLR,
> > + ~0);
> >
> > /* Release all bridges from reset state */
> > clrbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST,
> > ~0);
> >
> > /* Poll until all idleack to 0 */
> > - while (readl(&system_manager_base->noc_idleack))
> > + while (readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEACK))
> > ;
> > } else {
> > /* set idle request to all bridges */
> > - writel(~0, &system_manager_base->noc_idlereq_set);
> > + writel(~0, socfpga_sysmgr_base +
> > SYSMGR_S10_NOC_IDLEREQ_SET);
> >
> > /* Enable the NOC timeout */
> > - writel(1, &system_manager_base->noc_timeout);
> > + writel(1, socfpga_sysmgr_base + SYSMGR_S10_NOC_TIMEOUT);
> >
> > /* Poll until all idleack to 1 */
> > - while ((readl(&system_manager_base->noc_idleack) ^
> > + while ((readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEACK)
> > ^
> > (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
> > ;
> >
> > /* Poll until all idlestatus to 1 */
> > - while ((readl(&system_manager_base->noc_idlestatus) ^
> > + while ((readl(socfpga_sysmgr_base +
> > SYSMGR_S10_NOC_IDLESTATUS) ^
> > (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
> > ;
> >
> > @@ -90,7 +88,7 @@ void socfpga_bridges_reset(int enable)
> > RSTMGR_BRGMODRST_FPGA2SOC_MASK));
> >
> > /* Disable NOC timeout */
> > - writel(0, &system_manager_base->noc_timeout);
> > + writel(0, socfpga_sysmgr_base + SYSMGR_S10_NOC_TIMEOUT);
> > }
> > }
> >
> > diff --git a/arch/arm/mach-socfpga/scan_manager.c
> > b/arch/arm/mach-socfpga/scan_manager.c
> > index 52175af48b..f1d5f69caa 100644
> > --- a/arch/arm/mach-socfpga/scan_manager.c
> > +++ b/arch/arm/mach-socfpga/scan_manager.c
> > @@ -31,8 +31,6 @@ static const struct socfpga_scan_manager
> > *scan_manager_base =
> > (void *)(SOCFPGA_SCANMGR_ADDRESS);
> > static const struct socfpga_freeze_controller *freeze_controller_base =
> > (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
> > -static struct socfpga_system_manager *sys_mgr_base =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> >
> > /**
> > * scan_chain_engine_is_idle() - Check if the JTAG scan chain is idle
> > @@ -218,7 +216,7 @@ u32 scan_mgr_get_fpga_id(void)
> > int ret;
> >
> > /* Enable HPS to talk to JTAG in the FPGA through the System
> > Manager */
> > - writel(0x1, &sys_mgr_base->scanmgrgrp_ctrl);
> > + writel(0x1, socfpga_sysmgr_base + SYSMGR_GEN5_SCANMGRGRP_CTRL);
> >
> > /* Enable port 7 */
> > writel(0x80, &scan_manager_base->en);
> > @@ -253,7 +251,7 @@ u32 scan_mgr_get_fpga_id(void)
> >
> > /* Disable all port */
> > writel(0, &scan_manager_base->en);
> > - writel(0, &sys_mgr_base->scanmgrgrp_ctrl);
> > + writel(0, socfpga_sysmgr_base + SYSMGR_GEN5_SCANMGRGRP_CTRL);
> >
> > return id;
> > }
> > diff --git a/arch/arm/mach-socfpga/spl_a10.c
> > b/arch/arm/mach-socfpga/spl_a10.c
> > index a0d80fd47e..ee811e4ee9 100644
> > --- a/arch/arm/mach-socfpga/spl_a10.c
> > +++ b/arch/arm/mach-socfpga/spl_a10.c
> > @@ -31,12 +31,9 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static const struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > u32 spl_boot_device(void)
> > {
> > - const u32 bsel = readl(&sysmgr_regs->bootinfo);
> > + const u32 bsel = readl(socfpga_sysmgr_base + SYSMGR_A10_BOOTINFO);
> >
> > switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
> > case 0x1: /* FPGA (HPS2FPGA Bridge) */
> > diff --git a/arch/arm/mach-socfpga/spl_gen5.c
> > b/arch/arm/mach-socfpga/spl_gen5.c
> > index 9ee053da3a..82d9fe0824 100644
> > --- a/arch/arm/mach-socfpga/spl_gen5.c
> > +++ b/arch/arm/mach-socfpga/spl_gen5.c
> > @@ -24,12 +24,9 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static const struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > u32 spl_boot_device(void)
> > {
> > - const u32 bsel = readl(&sysmgr_regs->bootinfo);
> > + const u32 bsel = readl(socfpga_sysmgr_base + SYSMGR_GEN5_BOOTINFO);
> >
> > switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
> > case 0x1: /* FPGA (HPS2FPGA Bridge) */
> > @@ -77,13 +74,13 @@ void board_init_f(ulong dummy)
> > * First C code to run. Clear fake OCRAM ECC first as SBE
> > * and DBE might triggered during power on
> > */
> > - reg = readl(&sysmgr_regs->eccgrp_ocram);
> > + reg = readl(socfpga_sysmgr_base + SYSMGR_GEN5_ECCGRP_OCRAM);
> > if (reg & SYSMGR_ECC_OCRAM_SERR)
> > writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
> > - &sysmgr_regs->eccgrp_ocram);
> > + socfpga_sysmgr_base + SYSMGR_GEN5_ECCGRP_OCRAM);
> > if (reg & SYSMGR_ECC_OCRAM_DERR)
> > writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
> > - &sysmgr_regs->eccgrp_ocram);
> > + socfpga_sysmgr_base + SYSMGR_GEN5_ECCGRP_OCRAM);
> >
> > socfpga_sdram_remap_zero();
> > socfpga_pl310_clear();
> > diff --git a/arch/arm/mach-socfpga/spl_s10.c
> > b/arch/arm/mach-socfpga/spl_s10.c
> > index 9a97a84e1e..16f19f901d 100644
> > --- a/arch/arm/mach-socfpga/spl_s10.c
> > +++ b/arch/arm/mach-socfpga/spl_s10.c
> > @@ -22,9 +22,6 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > u32 spl_boot_device(void)
> > {
> > /* TODO: Get from SDM or handoff */
> > @@ -129,7 +126,8 @@ void board_init_f(ulong dummy)
> >
> > #ifdef CONFIG_HW_WATCHDOG
> > /* Ensure watchdog is paused when debugging is happening */
> > - writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
> > + writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
> > + socfpga_sysmgr_base + SYSMGR_S10_WDDBG);
> >
> > /* Enable watchdog before initializing the HW */
> > socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
> > @@ -157,8 +155,10 @@ void board_init_f(ulong dummy)
> > cm_print_clock_quick_summary();
> >
> > /* enable non-secure interface to DMA330 DMA and peripherals */
> > - writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma);
> > - writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph);
> > + writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS,
> > + socfpga_sysmgr_base + SYSMGR_S10_DMA);
> > + writel(SYSMGR_DMAPERIPH_ALL_NS,
> > + socfpga_sysmgr_base + SYSMGR_S10_DMA_PERIPH);
> >
> > spl_disable_firewall_l4_per();
> >
> > diff --git a/arch/arm/mach-socfpga/system_manager_gen5.c
> > b/arch/arm/mach-socfpga/system_manager_gen5.c
> > index 9d04aea2a8..1053a47201 100644
> > --- a/arch/arm/mach-socfpga/system_manager_gen5.c
> > +++ b/arch/arm/mach-socfpga/system_manager_gen5.c
> > @@ -8,9 +8,6 @@
> > #include <asm/arch/system_manager.h>
> > #include <asm/arch/fpga_manager.h>
> >
> > -static struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > /*
> > * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
> > * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
> > @@ -21,30 +18,39 @@ static void populate_sysmgr_fpgaintf_module(void)
> > u32 handoff_val = 0;
> >
> > /* ISWGRP_HANDOFF_FPGAINTF */
> > - writel(0, &sysmgr_regs->iswgrp_handoff[2]);
> > + writel(0, socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(2));
> >
> > /* Enable the signal for those HPS peripherals that use FPGA. */
> > - if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_NAND_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_NAND;
> > - if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_RGMII1_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_EMAC1;
> > - if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_SDMMC_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_SDMMC;
> > - if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_RGMII0_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_EMAC0;
> > - if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_SPIM0_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_SPIM0;
> > - if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_SPIM1_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_SPIM1;
> >
> > /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
> > based on pinmux setting */
> > - setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val);
> > + setbits_le32(socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(2),
> > + handoff_val);
> >
> > - handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]);
> > + handoff_val = readl(socfpga_sysmgr_base +
> > + SYSMGR_ISWGRP_HANDOFF_OFFSET(2));
> > if (fpgamgr_test_fpga_ready()) {
> > /* Enable the required signals only */
> > - writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module);
> > + writel(handoff_val,
> > + socfpga_sysmgr_base + SYSMGR_GEN5_FPGAINFGRP_MODULE);
> > }
> > }
> >
> > @@ -53,7 +59,7 @@ static void populate_sysmgr_fpgaintf_module(void)
> > */
> > void sysmgr_pinmux_init(void)
> > {
> > - u32 regs = (u32)&sysmgr_regs->emacio[0];
> > + u32 regs = (u32)socfpga_sysmgr_base + SYSMGR_GEN5_EMACIO;
> > const u8 *sys_mgr_init_table;
> > unsigned int len;
> > int i;
> > @@ -74,9 +80,9 @@ void sysmgr_pinmux_init(void)
> > void sysmgr_config_warmrstcfgio(int enable)
> > {
> > if (enable)
> > - setbits_le32(&sysmgr_regs->romcodegrp_ctrl,
> > + setbits_le32(socfpga_sysmgr_base +
> > SYSMGR_GEN5_ROMCODEGRP_CTRL,
> > SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
> > else
> > - clrbits_le32(&sysmgr_regs->romcodegrp_ctrl,
> > + clrbits_le32(socfpga_sysmgr_base +
> > SYSMGR_GEN5_ROMCODEGRP_CTRL,
> > SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
> > }
> > diff --git a/arch/arm/mach-socfpga/system_manager_s10.c
> > b/arch/arm/mach-socfpga/system_manager_s10.c
> > index 122828c9ce..c046bb17c9 100644
> > --- a/arch/arm/mach-socfpga/system_manager_s10.c
> > +++ b/arch/arm/mach-socfpga/system_manager_s10.c
> > @@ -10,9 +10,6 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > /*
> > * Configure all the pin muxes
> > */
> > @@ -32,24 +29,31 @@ void populate_sysmgr_fpgaintf_module(void)
> > u32 handoff_val = 0;
> >
> > /* Enable the signal for those HPS peripherals that use FPGA. */
> > - if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_S10_NAND_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_NAND;
> > - if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_S10_SDMMC_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_SDMMC;
> > - if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_S10_SPIM0_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_SPIM0;
> > - if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_S10_SPIM1_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_SPIM1;
> > - writel(handoff_val, &sysmgr_regs->fpgaintf_en_2);
> > + writel(handoff_val, socfpga_sysmgr_base + SYSMGR_S10_FPGAINTF_EN2);
> >
> > handoff_val = 0;
> > - if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC0_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_EMAC0;
> > - if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC1_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_EMAC1;
> > - if (readl(&sysmgr_regs->rgmii2usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC2_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_EMAC2;
> > - writel(handoff_val, &sysmgr_regs->fpgaintf_en_3);
> > + writel(handoff_val, socfpga_sysmgr_base + SYSMGR_S10_FPGAINTF_EN3);
> > }
> >
> > /*
> > @@ -64,14 +68,16 @@ void populate_sysmgr_pinmux(void)
> > sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len);
> > for (i = 0; i < len; i = i + 2) {
> > writel(sys_mgr_table_u32[i + 1],
> > - sys_mgr_table_u32[i] + (u8
> > *)&sysmgr_regs->pinsel0[0]);
> > + sys_mgr_table_u32[i] +
> > + (u8 *)socfpga_sysmgr_base + SYSMGR_S10_PINSEL0);
> > }
> >
> > /* setup the pin ctrl */
> > sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len);
> > for (i = 0; i < len; i = i + 2) {
> > writel(sys_mgr_table_u32[i + 1],
> > - sys_mgr_table_u32[i] + (u8
> > *)&sysmgr_regs->ioctrl0[0]);
> > + sys_mgr_table_u32[i] +
> > + (u8 *)socfpga_sysmgr_base + SYSMGR_S10_IOCTRL0);
> > }
> >
> > /* setup the fpga use */
> > @@ -79,13 +85,14 @@ void populate_sysmgr_pinmux(void)
> > for (i = 0; i < len; i = i + 2) {
> > writel(sys_mgr_table_u32[i + 1],
> > sys_mgr_table_u32[i] +
> > - (u8 *)&sysmgr_regs->rgmii0usefpga);
> > + (u8 *)socfpga_sysmgr_base +
> > SYSMGR_S10_EMAC0_USEFPGA);
> > }
> >
> > /* setup the IO delay */
> > sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len);
> > for (i = 0; i < len; i = i + 2) {
> > writel(sys_mgr_table_u32[i + 1],
> > - sys_mgr_table_u32[i] + (u8
> > *)&sysmgr_regs->iodelay0[0]);
> > + sys_mgr_table_u32[i] +
> > + (u8 *)socfpga_sysmgr_base + SYSMGR_S10_IODELAY0);
> > }
> > }
> > diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> > b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> > index 7cafc7dcfc..c9570fea38 100644
> > --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> > +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> > @@ -10,9 +10,6 @@
> > #include <asm/arch/handoff_s10.h>
> > #include <asm/arch/system_manager.h>
> >
> > -static const struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > const struct cm_config * const cm_get_default_config(void)
> > {
> > struct cm_config *cm_handoff_cfg = (struct cm_config *)
> > @@ -38,9 +35,9 @@ const unsigned int cm_get_osc_clk_hz(void)
> > #ifdef CONFIG_SPL_BUILD
> > u32 clock = readl(S10_HANDOFF_CLOCK_OSC);
> >
> > - writel(clock, &sysmgr_regs->boot_scratch_cold1);
> > + writel(clock, socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD1);
> > #endif
> > - return readl(&sysmgr_regs->boot_scratch_cold1);
> > + return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD1);
> > }
> >
> > const unsigned int cm_get_intosc_clk_hz(void)
> > @@ -53,7 +50,7 @@ const unsigned int cm_get_fpga_clk_hz(void)
> > #ifdef CONFIG_SPL_BUILD
> > u32 clock = readl(S10_HANDOFF_CLOCK_FPGA);
> >
> > - writel(clock, &sysmgr_regs->boot_scratch_cold2);
> > + writel(clock, socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD2);
> > #endif
> > - return readl(&sysmgr_regs->boot_scratch_cold2);
> > + return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD2);
> > }
> > diff --git a/drivers/ddr/altera/sdram_gen5.c
> > b/drivers/ddr/altera/sdram_gen5.c
> > index fcd89b619d..46a5c466a7 100644
> > --- a/drivers/ddr/altera/sdram_gen5.c
> > +++ b/drivers/ddr/altera/sdram_gen5.c
> > @@ -40,9 +40,6 @@ struct sdram_prot_rule {
> > u32 hi_prot_id;
> > };
> >
> > -static struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl
> > *sdr_ctrl);
> >
> > /**
> > @@ -455,12 +452,13 @@ int sdram_mmr_init_full(struct socfpga_sdr_ctrl
> > *sdr_ctrl,
> > SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
> > int ret;
> >
> > - writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
> > + writel(rows, socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
> >
> > sdr_load_regs(sdr_ctrl, cfg);
> >
> > /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
> > - writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
> > + writel(cfg->fpgaport_rst,
> > + socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(3));
> >
> > /* only enable if the FPGA is programmed */
> > if (fpgamgr_test_fpga_ready()) {
> > @@ -516,7 +514,7 @@ static unsigned long sdram_calculate_size(struct
> > socfpga_sdr_ctrl *sdr_ctrl)
> > * since the FB specifies we modify ROWBITs to work around SDRAM
> > * controller issue.
> > */
> > - row = readl(&sysmgr_regs->iswgrp_handoff[4]);
> > + row = readl(socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
> > if (row == 0)
> > row = rowbits;
> > /*
> > diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
> > index 56cbbac9fe..d5812f2fd7 100644
> > --- a/drivers/ddr/altera/sdram_s10.c
> > +++ b/drivers/ddr/altera/sdram_s10.c
> > @@ -32,9 +32,6 @@ struct altera_sdram_platdata {
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static const struct socfpga_system_manager *sysmgr_regs =
> > - (void *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) |
> > (R))
> >
> > #define PGTABLE_OFF 0x4000
> > @@ -150,7 +147,8 @@ static int emif_reset(struct altera_sdram_platdata
> > *plat)
> >
> > static int poll_hmc_clock_status(void)
> > {
> > - return wait_for_bit_le32(&sysmgr_regs->hmc_clk,
> > + return wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
> > + SYSMGR_S10_HMC_CLK),
> > SYSMGR_HMC_CLK_STATUS_MSK, true, 1000,
> > false);
> > }
> >
> > diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
> > index 5fb9d6a191..743326cdb3 100644
> > --- a/drivers/fpga/socfpga_arria10.c
> > +++ b/drivers/fpga/socfpga_arria10.c
> > @@ -30,9 +30,6 @@ DECLARE_GLOBAL_DATA_PTR;
> > static const struct socfpga_fpga_manager *fpga_manager_base =
> > (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> >
> > -static const struct socfpga_system_manager *system_manager_base =
> > - (void *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > static void fpgamgr_set_cd_ratio(unsigned long ratio);
> >
> > static uint32_t fpgamgr_get_msel(void)
> > @@ -818,7 +815,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const
> > void *buf, size_t bsize,
> > }
> >
> > /* Disable all signals from HPS peripheral controller to FPGA */
> > - writel(0, &system_manager_base->fpgaintf_en_global);
> > + writel(0, socfpga_sysmgr_base + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
> >
> > /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
> > socfpga_bridges_reset();
> > @@ -910,7 +907,7 @@ int socfpga_load(Altera_desc *desc, const void
> > *rbf_data, size_t rbf_size)
> > memset(&rbfinfo, 0, sizeof(rbfinfo));
> >
> > /* Disable all signals from hps peripheral controller to fpga */
> > - writel(0, &system_manager_base->fpgaintf_en_global);
> > + writel(0, socfpga_sysmgr_base + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
> >
> > /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
> > socfpga_bridges_reset();
> > diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c
> > index 6d16e0b37f..2b98572742 100644
> > --- a/drivers/fpga/socfpga_gen5.c
> > +++ b/drivers/fpga/socfpga_gen5.c
> > @@ -15,8 +15,6 @@
> >
> > static struct socfpga_fpga_manager *fpgamgr_regs =
> > (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> > -static struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> >
> > /* Set CD ratio */
> > static void fpgamgr_set_cd_ratio(unsigned long ratio)
> > @@ -214,7 +212,7 @@ int socfpga_load(Altera_desc *desc, const void
> > *rbf_data, size_t rbf_size)
> > /* Prior programming the FPGA, all bridges need to be shut off */
> >
> > /* Disable all signals from hps peripheral controller to fpga */
> > - writel(0, &sysmgr_regs->fpgaintfgrp_module);
> > + writel(0, socfpga_sysmgr_base + SYSMGR_GEN5_FPGAINFGRP_MODULE);
> >
> > /* Disable all signals from FPGA to HPS SDRAM */
> > #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
> > diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
> > index 739c1629a2..bdcd568d60 100644
> > --- a/drivers/mmc/socfpga_dw_mmc.c
> > +++ b/drivers/mmc/socfpga_dw_mmc.c
> > @@ -20,8 +20,6 @@ DECLARE_GLOBAL_DATA_PTR;
> >
> > static const struct socfpga_clock_manager *clock_manager_base =
> > (void *)SOCFPGA_CLKMGR_ADDRESS;
> > -static const struct socfpga_system_manager *system_manager_base =
> > - (void *)SOCFPGA_SYSMGR_ADDRESS;
> >
> > struct socfpga_dwmci_plat {
> > struct mmc_config cfg;
> > @@ -61,10 +59,10 @@ static void socfpga_dwmci_clksel(struct dwmci_host
> > *host)
> >
> > debug("%s: drvsel %d smplsel %d\n", __func__,
> > priv->drvsel, priv->smplsel);
> > - writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
> > + writel(sdmmc_mask, socfpga_sysmgr_base + SYSMGR_SDMMC);
> >
> > debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
> > - readl(&system_manager_base->sdmmcgrp_ctrl));
> > + readl(socfpga_sysmgr_base + SYSMGR_SDMMC));
> >
> > /* Enable SDMMC clock */
> > setbits_le32(&clock_manager_base->per_pll.en,
> > --
> > 2.19.0
> >
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