From: Dalon Westergreen <dalon.westergr...@intel.com> Sync devicetree from 5.2 kernel.
Signed-off-by: Dalon Westergreen <dalon.westergr...@intel.com> --- arch/arm/dts/socfpga_arria10.dtsi | 104 ++++++++++--------- arch/arm/dts/socfpga_arria10_socdk.dtsi | 75 +++++++------ arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 53 +--------- 3 files changed, 100 insertions(+), 132 deletions(-) diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index c11a5c0cc1..b175e05735 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright Altera Corporation (C) 2014. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. */ #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -21,11 +10,6 @@ #address-cells = <1>; #size-cells = <1>; - chosen { - tick-timer = &timer2; - u-boot,dm-pre-reloc; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -60,7 +44,6 @@ device_type = "soc"; interrupt-parent = <&intc>; ranges; - u-boot,dm-pre-reloc; amba { compatible = "simple-bus"; @@ -85,6 +68,7 @@ #dma-requests = <32>; clocks = <&l4_main_clk>; clock-names = "apb_pclk"; + microcode-cached; }; }; @@ -99,35 +83,29 @@ clkmgr@ffd04000 { compatible = "altr,clk-mgr"; reg = <0xffd04000 0x1000>; - u-boot,dm-pre-reloc; clocks { #address-cells = <1>; #size-cells = <0>; - u-boot,dm-pre-reloc; cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { #clock-cells = <0>; compatible = "fixed-clock"; - u-boot,dm-pre-reloc; }; cb_intosc_ls_clk: cb_intosc_ls_clk { #clock-cells = <0>; compatible = "fixed-clock"; - u-boot,dm-pre-reloc; }; f2s_free_clk: f2s_free_clk { #clock-cells = <0>; compatible = "fixed-clock"; - u-boot,dm-pre-reloc; }; osc1: osc1 { #clock-cells = <0>; compatible = "fixed-clock"; - u-boot,dm-pre-reloc; }; main_pll: main_pll@40 { @@ -138,7 +116,6 @@ clocks = <&osc1>, <&cb_intosc_ls_clk>, <&f2s_free_clk>; reg = <0x40>; - u-boot,dm-pre-reloc; main_mpu_base_clk: main_mpu_base_clk { #clock-cells = <0>; @@ -152,7 +129,6 @@ compatible = "altr,socfpga-a10-perip-clk"; clocks = <&main_pll>; div-reg = <0x144 0 11>; - u-boot,dm-pre-reloc; }; main_emaca_clk: main_emaca_clk@68 { @@ -228,7 +204,6 @@ clocks = <&osc1>, <&cb_intosc_ls_clk>, <&f2s_free_clk>, <&main_periph_ref_clk>; reg = <0xC0>; - u-boot,dm-pre-reloc; peri_mpu_base_clk: peri_mpu_base_clk { #clock-cells = <0>; @@ -242,7 +217,6 @@ compatible = "altr,socfpga-a10-perip-clk"; clocks = <&periph_pll>; div-reg = <0x144 16 11>; - u-boot,dm-pre-reloc; }; peri_emaca_clk: peri_emaca_clk@e8 { @@ -318,7 +292,6 @@ <&osc1>, <&cb_intosc_hs_div2_clk>, <&f2s_free_clk>; reg = <0x64>; - u-boot,dm-pre-reloc; }; s2f_user1_free_clk: s2f_user1_free_clk@104 { @@ -345,7 +318,6 @@ compatible = "altr,socfpga-a10-perip-clk"; clocks = <&noc_free_clk>; fixed-divider = <4>; - u-boot,dm-pre-reloc; }; l4_main_clk: l4_main_clk { @@ -395,13 +367,28 @@ clk-gate = <0xC8 11>; }; - nand_clk: nand_clk { + nand_x_clk: nand_x_clk { #clock-cells = <0>; compatible = "altr,socfpga-a10-gate-clk"; clocks = <&l4_mp_clk>; clk-gate = <0xC8 10>; }; + nand_ecc_clk: nand_ecc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&nand_x_clk>; + clk-gate = <0xC8 10>; + }; + + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&nand_x_clk>; + fixed-divider = <4>; + clk-gate = <0xC8 10>; + }; + spi_m_clk: spi_m_clk { #clock-cells = <0>; compatible = "altr,socfpga-a10-gate-clk"; @@ -496,11 +483,11 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xffc02900 0x100>; + resets = <&rst GPIO0_RESET>; status = "disabled"; porta: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; - bank-name = "porta"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <29>; @@ -516,11 +503,11 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xffc02a00 0x100>; + resets = <&rst GPIO1_RESET>; status = "disabled"; portb: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; - bank-name = "portb"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <29>; @@ -536,11 +523,11 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xffc02b00 0x100>; + resets = <&rst GPIO2_RESET>; status = "disabled"; portc: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; - bank-name = "portc"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <27>; @@ -568,7 +555,6 @@ interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; resets = <&rst I2C0_RESET>; - reset-names = "i2c"; status = "disabled"; }; @@ -580,7 +566,6 @@ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; resets = <&rst I2C1_RESET>; - reset-names = "i2c"; status = "disabled"; }; @@ -592,7 +577,6 @@ interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; resets = <&rst I2C2_RESET>; - reset-names = "i2c"; status = "disabled"; }; @@ -604,7 +588,6 @@ interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; resets = <&rst I2C3_RESET>; - reset-names = "i2c"; status = "disabled"; }; @@ -616,7 +599,19 @@ interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; resets = <&rst I2C4_RESET>; - reset-names = "i2c"; + status = "disabled"; + }; + + spi0: spi@ffda4000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda4000 0x100>; + interrupts = <0 101 4>; + num-cs = <4>; + /*32bit_access;*/ + clocks = <&spi_m_clk>; + resets = <&rst SPIM0_RESET>; status = "disabled"; }; @@ -626,16 +621,16 @@ #size-cells = <0>; reg = <0xffda5000 0x100>; interrupts = <0 102 4>; - num-chipselect = <4>; - bus-num = <0>; + num-cs = <4>; /*32bit_access;*/ tx-dma-channel = <&pdma 16>; rx-dma-channel = <&pdma 17>; clocks = <&spi_m_clk>; + resets = <&rst SPIM1_RESET>; status = "disabled"; }; - sdr: sdr@ffc25000 { + sdr: sdr@ffcfb100 { compatible = "altr,sdr-ctl", "syscon"; reg = <0xffcfb100 0x80>; }; @@ -667,13 +662,13 @@ nand: nand@ffb90000 { #address-cells = <1>; #size-cells = <1>; - compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand"; - reg = <0xffb90000 0x20>, - <0xffb80000 0x1000>; + compatible = "altr,socfpga-denali-nand"; + reg = <0xffb90000 0x72000>, + <0xffb80000 0x10000>; reg-names = "nand_data", "denali_reg"; interrupts = <0 99 4>; - dma-mask = <0xffffffff>; - clocks = <&nand_clk>; + clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; + clock-names = "nand", "nand_x", "ecc"; resets = <&rst NAND_RESET>; status = "disabled"; }; @@ -759,6 +754,7 @@ cdns,fifo-width = <4>; cdns,trigger-address = <0x00000000>; clocks = <&qspi_clk>; + resets = <&rst QSPI_RESET>; status = "disabled"; }; @@ -767,7 +763,6 @@ compatible = "altr,rst-mgr"; reg = <0xffd05000 0x100>; altr,modrst-offset = <0x20>; - u-boot,dm-pre-reloc; }; scu: snoop-control-unit@ffffc000 { @@ -785,7 +780,7 @@ timer@ffffc600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xffffc600 0x100>; - interrupts = <1 13 0xf04>; + interrupts = <1 13 0xf01>; clocks = <&mpu_periph_clk>; }; @@ -795,6 +790,8 @@ reg = <0xffc02700 0x100>; clocks = <&l4_sp_clk>; clock-names = "timer"; + resets = <&rst SPTIMER0_RESET>; + reset-names = "timer"; }; timer1: timer1@ffc02800 { @@ -803,6 +800,8 @@ reg = <0xffc02800 0x100>; clocks = <&l4_sp_clk>; clock-names = "timer"; + resets = <&rst SPTIMER1_RESET>; + reset-names = "timer"; }; timer2: timer2@ffd00000 { @@ -811,7 +810,8 @@ reg = <0xffd00000 0x100>; clocks = <&l4_sys_free_clk>; clock-names = "timer"; - u-boot,dm-pre-reloc; + resets = <&rst L4SYSTIMER0_RESET>; + reset-names = "timer"; }; timer3: timer3@ffd00100 { @@ -820,6 +820,8 @@ reg = <0xffd01000 0x100>; clocks = <&l4_sys_free_clk>; clock-names = "timer"; + resets = <&rst L4SYSTIMER1_RESET>; + reset-names = "timer"; }; uart0: serial0@ffc02000 { @@ -881,6 +883,7 @@ reg = <0xffd00200 0x100>; interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sys_free_clk>; + resets = <&rst L4WD0_RESET>; status = "disabled"; }; @@ -889,6 +892,7 @@ reg = <0xffd00300 0x100>; interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sys_free_clk>; + resets = <&rst L4WD1_RESET>; status = "disabled"; }; }; diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi index 6e5578d7bd..1ff37b89b1 100644 --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi @@ -1,20 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2015 Altera Corporation <www.altera.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ - #include "socfpga_arria10.dtsi" / { @@ -24,7 +11,6 @@ aliases { ethernet0 = &gmac0; serial0 = &uart1; - i2c0 = &i2c1; }; chosen { @@ -36,7 +22,6 @@ name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ - u-boot,dm-pre-reloc; }; a10leds { @@ -63,8 +48,21 @@ }; }; + ref_033v: 033-v-ref { + compatible = "regulator-fixed"; + regulator-name = "0.33V"; + regulator-min-microvolt = <330000>; + regulator-max-microvolt = <330000>; + }; + soc { - u-boot,dm-pre-reloc; + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; }; }; @@ -123,6 +121,10 @@ compatible = "altr,a10sr-reset"; #reset-cells = <1>; }; + + ps_alarm { + compatible = "altr,a10sr-hwmon"; + }; }; }; @@ -137,6 +139,26 @@ i2c-sda-falling-time-ns = <6000>; i2c-scl-falling-time-ns = <6000>; + adc@14 { + compatible = "lltc,ltc2497"; + reg = <0x14>; + vref-supply = <&ref_033v>; + }; + + adc@16 { + compatible = "lltc,ltc2497"; + reg = <0x16>; + vref-supply = <&ref_033v>; + }; + + lcd: lcd@28 { + compatible = "newhaven,nhd-0216k3z-nsw-bbw"; + reg = <0x28>; + height = <2>; + width = <16>; + brightness = <8>; + }; + eeprom@51 { compatible = "atmel,24c32"; reg = <0x51>; @@ -148,6 +170,11 @@ reg = <0x68>; }; + max@4c { + compatible = "max1619"; + reg = <0x4c>; + }; + ltc@5c { compatible = "ltc2977"; reg = <0x5c>; @@ -155,7 +182,6 @@ }; &uart1 { - u-boot,dm-pre-reloc; status = "okay"; }; @@ -167,16 +193,3 @@ &watchdog1 { status = "okay"; }; - -/* Clock available early */ -&main_periph_ref_clk { - u-boot,dm-pre-reloc; -}; - -&l4_mp_clk { - u-boot,dm-pre-reloc; -}; - -&l4_sp_clk { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts index d6b6c2ddc0..64dc0799f3 100644 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts @@ -1,47 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2014-2015 Altera Corporation <www.altera.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ /dts-v1/; #include "socfpga_arria10_socdk.dtsi" -#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi" -#include "socfpga_arria10_handoff_u-boot.dtsi" - -/ { - chosen { - firmware-loader = <&fs_loader0>; - }; - - fs_loader0: fs-loader { - u-boot,dm-pre-reloc; - compatible = "u-boot,fs-loader"; - phandlepart = <&mmc 1>; - }; -}; - -&fpga_mgr { - u-boot,dm-pre-reloc; - altr,bitstream = "fit_spl_fpga.itb"; -}; &mmc { - u-boot,dm-pre-reloc; status = "okay"; - num-slots = <1>; cap-sd-highspeed; + cap-mmc-highspeed; broken-cd; bus-width = <4>; }; @@ -57,20 +25,3 @@ <48 IRQ_TYPE_LEVEL_HIGH>; }; }; - -/* Clock available early */ -&main_sdmmc_clk { - u-boot,dm-pre-reloc; -}; - -&peri_sdmmc_clk { - u-boot,dm-pre-reloc; -}; - -&sdmmc_free_clk { - u-boot,dm-pre-reloc; -}; - -&sdmmc_clk { - u-boot,dm-pre-reloc; -}; -- 2.21.0 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
