On Mon, Oct 7, 2019 at 12:08 AM Bin Meng <bmeng...@gmail.com> wrote: > > On Wed, Sep 25, 2019 at 10:58 PM Simon Glass <s...@chromium.org> wrote: > > > > This code appears in a few places, so move it to a common file. > > > > Signed-off-by: Simon Glass <s...@chromium.org> > > --- > > > > arch/x86/cpu/broadwell/cpu_full.c | 20 +------------------- > > arch/x86/cpu/intel_common/cpu.c | 22 ++++++++++++++++++++++ > > arch/x86/cpu/ivybridge/model_206ax.c | 25 +++---------------------- > > arch/x86/include/asm/cpu_common.h | 11 +++++++++++ > > 4 files changed, 37 insertions(+), 41 deletions(-) > > > > diff --git a/arch/x86/cpu/broadwell/cpu_full.c > > b/arch/x86/cpu/broadwell/cpu_full.c > > index 0e3d8781392..d1f3c07109f 100644 > > --- a/arch/x86/cpu/broadwell/cpu_full.c > > +++ b/arch/x86/cpu/broadwell/cpu_full.c > > @@ -495,24 +495,6 @@ static void configure_misc(void) > > msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr); > > } > > > > -static void configure_thermal_target(struct udevice *dev) > > -{ > > - int tcc_offset; > > - msr_t msr; > > - > > - tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), > > - "intel,tcc-offset", 0); > > "intel,tcc-offset" removed > > > - > > - /* Set TCC activaiton offset if supported */ > > - msr = msr_read(MSR_PLATFORM_INFO); > > - if ((msr.lo & (1 << 30)) && tcc_offset) { > > - msr = msr_read(MSR_TEMPERATURE_TARGET); > > - msr.lo &= ~(0xf << 24); /* Bits 27:24 */ > > - msr.lo |= (tcc_offset & 0xf) << 24; > > - msr_write(MSR_TEMPERATURE_TARGET, msr); > > - } > > -} > > - > > static void configure_dca_cap(void) > > { > > struct cpuid_result cpuid_regs; > > @@ -562,7 +544,7 @@ static void cpu_core_init(struct udevice *dev) > > configure_misc(); > > > > /* Thermal throttle activation offset */ > > - configure_thermal_target(dev); > > + cpu_configure_thermal_target(dev); > > > > /* Enable Direct Cache Access */ > > configure_dca_cap(); > > diff --git a/arch/x86/cpu/intel_common/cpu.c > > b/arch/x86/cpu/intel_common/cpu.c > > index 3a0d505a321..7d0ed73b4b6 100644 > > --- a/arch/x86/cpu/intel_common/cpu.c > > +++ b/arch/x86/cpu/intel_common/cpu.c > > @@ -123,3 +123,25 @@ int cpu_intel_get_info(struct cpu_info *info, int bclk) > > > > return 0; > > } > > + > > +int cpu_configure_thermal_target(struct udevice *dev) > > +{ > > + u32 tcc_offset; > > + msr_t msr; > > + int ret; > > + > > + ret = dev_read_u32(dev, "tcc-offset", &tcc_offset); > > "tcc-offset" added, so I wonder how this commit could avoid breaking > broadwell? But I see no dts file provides "tcc-offset", or > "intel,tcc-offset" neither. Probably not a problem. > > > + if (!ret) > > + return -ENOENT; > > + > > + /* Set TCC activaiton offset if supported */ > > + msr = msr_read(MSR_PLATFORM_INFO); > > + if (msr.lo & (1 << 30)) { > > + msr = msr_read(MSR_TEMPERATURE_TARGET); > > + msr.lo &= ~(0xf << 24); /* Bits 27:24 */ > > + msr.lo |= (tcc_offset & 0xf) << 24; > > + msr_write(MSR_TEMPERATURE_TARGET, msr); > > + } > > + > > + return 0; > > +} > > diff --git a/arch/x86/cpu/ivybridge/model_206ax.c > > b/arch/x86/cpu/ivybridge/model_206ax.c > > index 68e78e9478b..ed66d2dd8d7 100644 > > --- a/arch/x86/cpu/ivybridge/model_206ax.c > > +++ b/arch/x86/cpu/ivybridge/model_206ax.c > > @@ -283,26 +283,6 @@ static void configure_c_states(void) > > msr_write(MSR_PP1_CURRENT_CONFIG, msr); > > } > > > > -static int configure_thermal_target(struct udevice *dev) > > -{ > > - int tcc_offset; > > - msr_t msr; > > - > > - tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), > > - "tcc-offset", 0); > > - > > - /* Set TCC activaiton offset if supported */ > > - msr = msr_read(MSR_PLATFORM_INFO); > > - if ((msr.lo & (1 << 30)) && tcc_offset) { > > - msr = msr_read(MSR_TEMPERATURE_TARGET); > > - msr.lo &= ~(0xf << 24); /* Bits 27:24 */ > > - msr.lo |= (tcc_offset & 0xf) << 24; > > - msr_write(MSR_TEMPERATURE_TARGET, msr); > > - } > > - > > - return 0; > > -} > > - > > static void configure_misc(void) > > { > > msr_t msr; > > @@ -414,10 +394,11 @@ static int model_206ax_init(struct udevice *dev) > > configure_misc(); > > > > /* Thermal throttle activation offset */ > > - ret = configure_thermal_target(dev); > > + ret = cpu_configure_thermal_target(dev); > > if (ret) { > > debug("Cannot set thermal target\n"); > > - return ret; > > + if (ret != -ENOENT) > > + return ret; > > } > > > > /* Enable Direct Cache Access */ > > diff --git a/arch/x86/include/asm/cpu_common.h > > b/arch/x86/include/asm/cpu_common.h > > index eb922da2ab8..a1fd7498741 100644 > > --- a/arch/x86/include/asm/cpu_common.h > > +++ b/arch/x86/include/asm/cpu_common.h > > @@ -40,4 +40,15 @@ int cpu_set_flex_ratio_to_tdp_nominal(void); > > */ > > int cpu_intel_get_info(struct cpu_info *info, int bclk_mz); > > > > +/** > > + * cpu_configure_thermal_target() - Set the thermal target for a CPU > > + * > > + * This looks up the tcc-offset property and uses it to set the > > + * MSR_TEMPERATURE_TARGET value. > > + * > > + * @dev: CPU device > > + * @return 0 if OK, -ENOENT if no target is given in device tree > > + */ > > +int cpu_configure_thermal_target(struct udevice *dev); > > + > > #endif > > -- > > Reviewed-by: Bin Meng <bmeng...@gmail.com>
applied to u-boot-x86/next, thanks! _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot