On Wed, Sep 04, 2019 at 04:01:38PM +0530, Lokesh Vutla wrote: > The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS) > subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within > the MCU domain, and the remaining two clusters are present in the > MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be > configured at boot time to be either run in a LockStep mode or in > an Asymmetric Multi Processing (AMP) fashion in Split-mode. These > subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal > memories for each core split between two banks - ATCM and BTCM > (further interleaved into two banks). There are some IP integration > differences from standard Arm R5 clusters such as the absence of > an ACP port, presence of an additional TI-specific Region Address > Translater (RAT) module for translating 32-bit CPU addresses into > larger system bus addresses etc. > > Add the DT nodes for these two MAIN domain R5F cluster/subsystems, > the two R5 cores are each added as child nodes to the corresponding > main cluster node. Configure SS0 in split mode an SS1 in lockstep mode, > with the ATCMs enabled to allow the R5 cores to execute code from DDR > with boot-strapping code from ATCM. > > Signed-off-by: Suman Anna <s-a...@ti.com> > Signed-off-by: Lokesh Vutla <lokeshvu...@ti.com>
Applied to u-boot/master, thanks! -- Tom
signature.asc
Description: PGP signature
_______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
