Hi Andy, On Tue, 22 Oct 2019 at 02:19, Andy Shevchenko <andy.shevche...@gmail.com> wrote: > > On Tue, Oct 22, 2019 at 1:54 AM Simon Glass <s...@chromium.org> wrote: > > On Mon, 21 Oct 2019 at 01:52, Andy Shevchenko <andy.shevche...@gmail.com> > > wrote: > > > On Mon, Oct 21, 2019 at 7:24 AM Simon Glass <s...@chromium.org> wrote: > > > > PCI(e) bus is present in a lot of SoCs (not exclusively x86). Perhaps > > > better idea is to have something like lib/pci.c with minimum support > > > for PCI type 1 and probably PCI type 2 accessors and other very basic > > > functions. > > > > I don't know of any use case for PCI in TPL on other platforms. > > > > x86 is I think unique in that it requires PCI to do anything. > > I don't think so. PCI is a core part of the SoC, indeed, though what > exactly do we need from it here? IO accessors to PCI configuration > space?
I mean that on other SoCs I am familiar with you can access peripherals through memory-mapped I/O. On x86 so far as I am aware you can't see any peripheral without doing some PCI config. Therefore PCI is 'more core' on x86 than others. For example on an Nvidia chip I am familiar with, you can do everything except enable the PCI network chip, which you wouldn't do in TPL. > > > For > > other platforms I am familiar with they can boot a fair way without > > it. > > Perhaps we may achieve the same here? > > > I do want to avoid the premature-optimisation problem, i.e. inventing > > new use cases that no one uses. The only thing we really know right > > now is that we need this for newer x86 platforms. Regards, Simon _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot