+
#ifdef CONFIG_SYS_L2_PL310
static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -145,6 +147,8 @@ void socfpga_fpga_add(void *fpga_desc)
int arch_cpu_init(void)
{
+ socfpga_get_manager_addr();
+
#ifdef CONFIG_HW_WATCHDOG
/*
* In case the watchdog is enabled, make sure to (re-)configure it
@@ -202,3 +206,31 @@ U_BOOT_CMD(bridge, 3, 1, do_bridge,
);
#endif
+
+static phys_addr_t socfpga_get_base_addr(const char *compat)
+{
+ const void *blob = gd->fdt_blob;
+ struct fdt_resource r;
+ int node;
+ int ret;
+
+ node = fdt_node_offset_by_compatible(blob, -1, compat);
+ if (node < 0)
+ return 0;
+
+ if (!fdtdec_get_is_enabled(blob, node))
+ return 0;
+
+ ret = fdt_get_resource(blob, node, "reg", 0, &r);
+ if (ret)
+ return 0;
+
+ return (phys_addr_t)r.start;
+}
+
+void socfpga_get_manager_addr(void)
+{
+ socfpga_rstmgr_base = socfpga_get_base_addr("altr,rst-mgr");
+ if (!socfpga_rstmgr_base)
+ hang();
+}
diff --git a/arch/arm/mach-socfpga/misc_gen5.c
b/arch/arm/mach-socfpga/misc_gen5.c
index 31681b799d..b39a66562d 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -206,8 +206,6 @@ int arch_early_init_r(void)
}
#ifndef CONFIG_SPL_BUILD
-static struct socfpga_reset_manager *reset_manager_base =
- (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
@@ -226,12 +224,13 @@ void do_bridge_reset(int enable, unsigned int mask)
writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
- writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
+ writel(iswgrp_handoff[0],
+ socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
writel(iswgrp_handoff[1], &nic301_regs->remap);
} else {
writel(0, &sysmgr_regs->fpgaintfgrp_module);
writel(0, &sdr_ctrl->fpgaport_rst);
- writel(0, &reset_manager_base->brg_mod_reset);
+ writel(0, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
writel(1, &nic301_regs->remap);
}
}
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c
b/arch/arm/mach-socfpga/reset_manager_arria10.c
index 471a3045af..4553653992 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -15,8 +15,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_reset_manager *reset_manager_base =
- (void *)SOCFPGA_RSTMGR_ADDRESS;
static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
@@ -63,14 +61,14 @@ static const struct bridge_cfg bridge_cfg_tbl[] = {
void socfpga_watchdog_disable(void)
{
/* assert reset for watchdog */
- setbits_le32(&reset_manager_base->per1modrst,
+ setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER1MODRST,
ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
}
/* Release NOC ddr scheduler from reset */
void socfpga_reset_deassert_noc_ddr_scheduler(void)
{
- clrbits_le32(&reset_manager_base->brgmodrst,
+ clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST,
ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
}
@@ -103,7 +101,7 @@ int socfpga_reset_deassert_bridges_handoff(void)
setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
/* Release bridges from reset state per handoff value */
- clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
+ clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST, mask_rstmgr);
/* Poll until all idleack to 0, timeout at 1000ms */
return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
@@ -113,7 +111,7 @@ int socfpga_reset_deassert_bridges_handoff(void)
/* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
void socfpga_reset_deassert_osc1wd0(void)
{
- clrbits_le32(&reset_manager_base->per1modrst,
+ clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER1MODRST,
ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
}
@@ -122,24 +120,24 @@ void socfpga_reset_deassert_osc1wd0(void)
*/
void socfpga_per_reset(u32 reset, int set)
{
- const u32 *reg;
+ unsigned long reg;
u32 rstmgr_bank = RSTMGR_BANK(reset);
switch (rstmgr_bank) {
case 0:
- reg = &reset_manager_base->mpumodrst;
+ reg = RSTMGR_A10_MPUMODRST;
break;
case 1:
- reg = &reset_manager_base->per0modrst;
+ reg = RSTMGR_A10_PER0MODRST;
break;
case 2:
- reg = &reset_manager_base->per1modrst;
+ reg = RSTMGR_A10_PER1MODRST;
break;
case 3:
- reg = &reset_manager_base->brgmodrst;
+ reg = RSTMGR_A10_BRGMODRST;
break;
case 4:
- reg = &reset_manager_base->sysmodrst;
+ reg = RSTMGR_A10_SYSMODRST;
break;
default:
@@ -147,9 +145,11 @@ void socfpga_per_reset(u32 reset, int set)
}
if (set)
- setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ setbits_le32(socfpga_rstmgr_base + reg,
+ 1 << RSTMGR_RESET(reset));
else
- clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ clrbits_le32(socfpga_rstmgr_base + reg,
+ 1 << RSTMGR_RESET(reset));
}
/*
@@ -174,11 +174,12 @@ void socfpga_per_reset_all(void)
ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
- writel(~l4wd0, &reset_manager_base->per1modrst);
- setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
+ writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_A10_PER1MODRST);
+ setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER0MODRST,
+ ~mask_ecc_ocp);
/* Finally disable the ECC_OCP */
- setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
+ setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER0MODRST, mask_ecc_ocp);
}
int socfpga_bridges_reset(void)
@@ -224,13 +225,13 @@ int socfpga_bridges_reset(void)
return ret;
/* Put all bridges (except NOR DDR scheduler) into reset state */
- setbits_le32(&reset_manager_base->brgmodrst,
+ setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST,
(ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
- ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
- ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
- ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
- ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
- ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
+ ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
+ ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
+ ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
+ ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
+ ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
/* Disable NOC timeout */
writel(0, &sysmgr_regs->noc_timeout);
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c
b/arch/arm/mach-socfpga/reset_manager_gen5.c
index 9a32f5abfe..ad31214711 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -10,32 +10,30 @@
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
-static const struct socfpga_reset_manager *reset_manager_base =
- (void *)SOCFPGA_RSTMGR_ADDRESS;
static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
/* Assert or de-assert SoCFPGA reset manager reset. */
void socfpga_per_reset(u32 reset, int set)
{
- const u32 *reg;
+ unsigned long reg;
u32 rstmgr_bank = RSTMGR_BANK(reset);
switch (rstmgr_bank) {
case 0:
- reg = &reset_manager_base->mpu_mod_reset;
+ reg = RSTMGR_GEN5_MPUMODRST;
break;
case 1:
- reg = &reset_manager_base->per_mod_reset;
+ reg = RSTMGR_GEN5_PERMODRST;
break;
case 2:
- reg = &reset_manager_base->per2_mod_reset;
+ reg = RSTMGR_GEN5_PER2MODRST;
break;
case 3:
- reg = &reset_manager_base->brg_mod_reset;
+ reg = RSTMGR_GEN5_BRGMODRST;
break;
case 4:
- reg = &reset_manager_base->misc_mod_reset;
+ reg = RSTMGR_GEN5_MISCMODRST;
break;
default:
@@ -43,9 +41,11 @@ void socfpga_per_reset(u32 reset, int set)
}
if (set)
- setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ setbits_le32(socfpga_rstmgr_base + reg,
+ 1 << RSTMGR_RESET(reset));
else
- clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ clrbits_le32(socfpga_rstmgr_base + reg,
+ 1 << RSTMGR_RESET(reset));
}
/*
@@ -57,8 +57,8 @@ void socfpga_per_reset_all(void)
{
const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
- writel(~l4wd0, &reset_manager_base->per_mod_reset);
- writel(0xffffffff, &reset_manager_base->per2_mod_reset);
+ writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_GEN5_PERMODRST);
+ writel(0xffffffff, socfpga_rstmgr_base + RSTMGR_GEN5_PER2MODRST);
}
#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
@@ -95,7 +95,7 @@ void socfpga_bridges_reset(int enable)
if (enable) {
/* brdmodrst */
- writel(0x7, &reset_manager_base->brg_mod_reset);
+ writel(0x7, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
writel(L3REGS_REMAP_OCRAM_MASK, SOCFPGA_L3REGS_ADDRESS);
} else {
socfpga_bridges_set_handoff_regs(false, false, false);
@@ -109,7 +109,7 @@ void socfpga_bridges_reset(int enable)
}
/* brdmodrst */
- writel(0, &reset_manager_base->brg_mod_reset);
+ writel(0, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
/* Remap the bridges into memory map */
writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm/mach-socfpga/reset_manager_s10.c
index 499a84aff5..b196d58d3d 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -12,31 +12,31 @@
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_reset_manager *reset_manager_base =
- (void *)SOCFPGA_RSTMGR_ADDRESS;
static const struct socfpga_system_manager *system_manager_base =
(void *)SOCFPGA_SYSMGR_ADDRESS;
/* Assert or de-assert SoCFPGA reset manager reset. */
void socfpga_per_reset(u32 reset, int set)
{
- const void *reg;
+ unsigned long reg;
if (RSTMGR_BANK(reset) == 0)
- reg = &reset_manager_base->mpumodrst;
+ reg = RSTMGR_S10_MPUMODRST;
else if (RSTMGR_BANK(reset) == 1)
- reg = &reset_manager_base->per0modrst;
+ reg = RSTMGR_S10_PER0MODRST;
else if (RSTMGR_BANK(reset) == 2)
- reg = &reset_manager_base->per1modrst;
+ reg = RSTMGR_S10_PER1MODRST;
else if (RSTMGR_BANK(reset) == 3)
- reg = &reset_manager_base->brgmodrst;
+ reg = RSTMGR_S10_BRGMODRST;
else /* Invalid reset register, do nothing */
return;
if (set)
- setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ setbits_le32(socfpga_rstmgr_base + reg,
+ 1 << RSTMGR_RESET(reset));
else
- clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ clrbits_le32(socfpga_rstmgr_base + reg,
+ 1 << RSTMGR_RESET(reset));
}
/*
@@ -50,9 +50,9 @@ void socfpga_per_reset_all(void)
/* disable all except OCP and l4wd0. OCP disable later */
writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
- &reset_manager_base->per0modrst);
- writel(~l4wd0, &reset_manager_base->per0modrst);
- writel(0xffffffff, &reset_manager_base->per1modrst);
+ socfpga_rstmgr_base + RSTMGR_S10_PER0MODRST);
+ writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_S10_PER0MODRST);
+ writel(0xffffffff, socfpga_rstmgr_base + RSTMGR_S10_PER1MODRST);
}
void socfpga_bridges_reset(int enable)
@@ -62,7 +62,7 @@ void socfpga_bridges_reset(int enable)
setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
/* Release all bridges from reset state */
- clrbits_le32(&reset_manager_base->brgmodrst, ~0);
+ clrbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST, ~0);
/* Poll until all idleack to 0 */
while (readl(&system_manager_base->noc_idleack))
@@ -85,9 +85,9 @@ void socfpga_bridges_reset(int enable)
;
/* Reset all bridges (except NOR DDR scheduler & F2S) */
- setbits_le32(&reset_manager_base->brgmodrst,
+ setbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST,
~(RSTMGR_BRGMODRST_DDRSCH_MASK |
- RSTMGR_BRGMODRST_FPGA2SOC_MASK));
+ RSTMGR_BRGMODRST_FPGA2SOC_MASK));
/* Disable NOC timeout */
writel(0, &system_manager_base->noc_timeout);
@@ -99,6 +99,6 @@ void socfpga_bridges_reset(int enable)
*/
int cpu_has_been_warmreset(void)
{
- return readl(&reset_manager_base->status) &
- RSTMGR_L4WD_MPU_WARMRESET_MASK;
+ return readl(socfpga_rstmgr_base + RSTMGR_S10_STATUS) &
+ RSTMGR_L4WD_MPU_WARMRESET_MASK;
}
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index b820cb0673..a0d80fd47e 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -106,6 +106,11 @@ void spl_board_init(void)
void board_init_f(ulong dummy)
{
+ if (spl_early_init())
+ hang();
+
+ socfpga_get_manager_addr();
+
dcache_disable();
socfpga_init_security_policies();
@@ -116,8 +121,6 @@ void board_init_f(ulong dummy)
socfpga_per_reset_all();
socfpga_watchdog_disable();
- spl_early_init();
-
/* Configure the clock based on handoff */
cm_basic_init(gd->fdt_blob);
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 47e63709ad..9ee053da3a 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -67,6 +67,12 @@ void board_init_f(ulong dummy)
int ret;
struct udevice *dev;
+ ret = spl_early_init();
+ if (ret)
+ hang();
+
+ socfpga_get_manager_addr();
+
/*
* First C code to run. Clear fake OCRAM ECC first as SBE
