[U-Boot] [PATCH v3] spi: cadence_qspi: support DM_CLK

[Simon Goldschmidt]

Support loading clk speed via DM instead of requiring ad-hoc code.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschm...@gmail.com>
---

Changes in v3:
- load ref_clk_hz only once in cadence_spi_ofdata_to_platdata instead
  of loading it every time in cadence_spi_write_speed

Changes in v2:
- check return value of clk_get_rate for error

 drivers/spi/cadence_qspi.c | 21 +++++++++++++++++++--
 drivers/spi/cadence_qspi.h |  1 +
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index e2e54cd277..8fd23a7702 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <fdtdec.h>
 #include <malloc.h>
@@ -24,10 +25,10 @@ static int cadence_spi_write_speed(struct udevice *bus, 
uint hz)
        struct cadence_spi_priv *priv = dev_get_priv(bus);
 
        cadence_qspi_apb_config_baudrate_div(priv->regbase,
-                                            CONFIG_CQSPI_REF_CLK, hz);
+                                            plat->ref_clk_hz, hz);
 
        /* Reconfigure delay timing if speed is changed. */
-       cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
+       cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
                               plat->tshsl_ns, plat->tsd2d_ns,
                               plat->tchsh_ns, plat->tslch_ns);
 
@@ -294,6 +295,8 @@ static int cadence_spi_ofdata_to_platdata(struct udevice 
*bus)
 {
        struct cadence_spi_platdata *plat = bus->platdata;
        ofnode subnode;
+       struct clk clk;
+       int ret;
 
        plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
        plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1);
@@ -325,6 +328,20 @@ static int cadence_spi_ofdata_to_platdata(struct udevice 
*bus)
        plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
        plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
 
+       ret = clk_get_by_index(bus, 0, &clk);
+       if (ret) {
+#ifdef CONFIG_CQSPI_REF_CLK
+               plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
+#else
+               return ret;
+#endif
+       } else {
+               plat->ref_clk_hz = clk_get_rate(&clk);
+               clk_free(&clk);
+               if (IS_ERR_VALUE(plat->ref_clk_hz))
+                       return plat->ref_clk_hz;
+       }
+
        debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
              __func__, plat->regbase, plat->ahbbase, plat->max_hz,
              plat->page_size);
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 20cceca239..99dee75bbd 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -16,6 +16,7 @@
 #define CQSPI_READ_CAPTURE_MAX_DELAY   16
 
 struct cadence_spi_platdata {
+       unsigned int    ref_clk_hz;
        unsigned int    max_hz;
        void            *regbase;
        void            *ahbbase;
-- 
2.20.1

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