> -----Original Message----- > From: Xiaowei Bao > Sent: 2019年5月22日 18:19 > To: Bin Meng <bmeng...@gmail.com>; Ramon Fried > <ramon.fr...@gmail.com>; Simon Glass <s...@chromium.org> > Cc: M.h. Lian <minghuan.l...@nxp.com>; Z.q. Hou <zhiqiang....@nxp.com>; > Mingkai Hu <mingkai...@nxp.com>; Hongbo Wang > <hongbo.w...@nxp.com>; York Sun <york....@nxp.com>; > u-boot@lists.denx.de; Jiafei Pan <jiafei....@nxp.com> > Subject: RE: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support > for ls2088 PCIe EP mode > > Hi Bin, > > -----Original Message----- > From: Bin Meng <bmeng...@gmail.com> > Sent: 2019年5月17日 10:31 > To: Xiaowei Bao <xiaowei....@nxp.com>; Ramon Fried > <ramon.fr...@gmail.com>; Simon Glass <s...@chromium.org> > Cc: M.h. Lian <minghuan.l...@nxp.com>; Z.q. Hou <zhiqiang....@nxp.com>; > Mingkai Hu <mingkai...@nxp.com>; Hongbo Wang > <hongbo.w...@nxp.com>; York Sun <york....@nxp.com>; > u-boot@lists.denx.de; Jiafei Pan <jiafei....@nxp.com> > Subject: Re: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support > for ls2088 PCIe EP mode > > Caution: EXT Email > > Hi Xiaowei, > > On Fri, May 17, 2019 at 10:23 AM Xiaowei Bao <xiaowei....@nxp.com> > wrote: > > > > > > > > -----Original Message----- > > From: Bin Meng <bmeng...@gmail.com> > > Sent: 2019年5月16日 19:58 > > To: Xiaowei Bao <xiaowei....@nxp.com> > > Cc: M.h. Lian <minghuan.l...@nxp.com>; Z.q. Hou > > <zhiqiang....@nxp.com>; Mingkai Hu <mingkai...@nxp.com>; Hongbo > Wang > > <hongbo.w...@nxp.com>; York Sun <york....@nxp.com>; > > u-boot@lists.denx.de; Jiafei Pan <jiafei....@nxp.com> > > Subject: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support > > for ls2088 PCIe EP mode > > > > Caution: EXT Email > > > > Hi, > > > > On Thu, May 16, 2019 at 7:02 PM Xiaowei Bao <xiaowei....@nxp.com> > wrote: > > > > > > From: Xiaowei Bao <xiaowei....@nxp.com> > > > > > > Signed-off-by: hongbo.wang <hongbo.w...@nxp.com> > > > Signed-off-by: Minghuan Lian <minghuan.l...@nxp.com> > > > Signed-off-by: Xiaowei Bao <xiaowei....@nxp.com> > > > --- > > > v2: > > > - Add the NXP copyright and make the function readability. > > > > > > drivers/pci/pcie_layerscape.c | 117 > +++++++++++++++++++++++++++-------------- > > > drivers/pci/pcie_layerscape.h | 19 +++++-- > > > 2 files changed, 91 insertions(+), 45 deletions(-) > > > > > > > Could you please support the PCIe EP mode using driver model? > > [Xiaowei Bao] do you mean that add a EP driver model to separate the RC > and EP with their respective drivers? > > That's correct. > > > The purpose of adding EP support under u-boot is to configure the size of > > the > BAR when the PCIE controller is used as an EP device, and to ensure that the > configuration space of the EP can be accessed, so that when the RC scans the > bus, the EP device can be scanned, and we also can do simple MEM read and > write verification through the md command in u-boot shell. > > When entering the kernel, the kernel has its own PCIE EP framework, which > will reinitialize the EP device, contain of the inbound and outbound window > configure, MSI configuration and so no. > > > > It's not kernel PCIe EP framework. Ramon Fried recently added PCIe EP uclass > support to U-Boot and you should add NXP layerscape PCIe EP driver using the > new EP uclass. > [Xiaowei Bao] OK, thanks, I will add NXP layerscape PCIe EP driver using the > new EP uclass.
Hi Bin and Ramon, Do you know how to test the EP device when use Ramon Fried EP framework patch, I don't know how to use it in u-boot, take our board as an example, we use the RCW to configure the PCIe controller work as EP or RC, never use the DTS, another issue, when our PCIe controller work in EP mode, we must set this controller is ready before RC scan the bus, our main purpose is that set the BAR size and make it ready in u-boot, ensure that the EP controller is ready when enter the kernel or other RC can scan the bus which the EP link, I am not sure whether should separate the EP and RC driver. Do you have any advice? Thanks Xiaowei > > See > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatchw > ork.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D104952&da > ta=02%7C01%7Cxiaowei.bao%40nxp.com%7Ca1e3da7d57a54520bd3008d6d > a6fbc4d%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C63693657 > 0769296107&sdata=5CnEujEtYGbeiBEyv4iY5dXAapdQ65wCh1vs0quSVT > Y%3D&reserved=0 > > Regards, > Bin _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
