Set up MTRRs for the FSP SDRAM regions to improve performance.
Signed-off-by: Simon Glass <s...@chromium.org>
Reviewed-by: Bin Meng <bmeng...@gmail.com>
---
Changes in v5:
- Fix FST typo
Changes in v4: None
Changes in v3:
- Move mtrr_add_request() call into this patch
Changes in v2: None
arch/x86/lib/fsp/fsp_dram.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index 3ede9b73fe..9ca898a0cd 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -8,6 +8,7 @@
#include <asm/fsp/fsp_support.h>
#include <asm/e820.h>
#include <asm/mrccache.h>
+#include <asm/mtrr.h>
#include <asm/post.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -60,6 +61,8 @@ int dram_init_banksize(void)
gd->bd->bi_dram[bank].start = res_desc->phys_start;
gd->bd->bi_dram[bank].size = res_desc->len;
+ mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
+ res_desc->len);
log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start,
gd->bd->bi_dram[bank].size);
}
@@ -68,6 +71,8 @@ int dram_init_banksize(void)
gd->bd->bi_dram[0].start = 0;
gd->bd->bi_dram[0].size = low_end;
+ mtrr_add_request(MTRR_TYPE_WRBACK, 0, low_end);
+
return 0;
}
--
2.24.0.432.g9d3f5f5b63-goog
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