On Wed,  4 Dec 2019 18:44:33 +0100
Giulio Benetti <giulio.bene...@benettiengineering.com> wrote:

> This driver assumes that lpuart clock is already enabled before
> probing but using DM only lpuart won't be automatically enabled so add
> clk_enable() when probing if CONFIG_CLK is defined.
> 
> Signed-off-by: Giulio Benetti <giulio.bene...@benettiengineering.com>
> ---
>  drivers/serial/serial_lpuart.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/serial/serial_lpuart.c
> b/drivers/serial/serial_lpuart.c index 4b0a964d1b..52bd2baf7d 100644
> --- a/drivers/serial/serial_lpuart.c
> +++ b/drivers/serial/serial_lpuart.c
> @@ -483,6 +483,19 @@ static int lpuart_serial_pending(struct udevice
> *dev, bool input) 
>  static int lpuart_serial_probe(struct udevice *dev)
>  {
> +#if CONFIG_IS_ENABLED(CLK)
> +     struct clk per_clk;
> +     int ret;
> +
> +     ret = clk_get_by_name(dev, "per", &per_clk);
> +     if (ret) {
> +             dev_err(dev, "Failed to get per clk: %d\n", ret);
> +             return ret;
> +     }
> +
> +     clk_enable(&per_clk);
> +#endif
> +

I think that this change will _silently_ break all boards which do have
CONFIG_CLK enabled (for some clocks/drivers), but did not yet provided
CCF definition for lpuart clock.

Was this series checked with travis-ci? 

For example:
https://travis-ci.org/lmajewski/u-boot-dfu/jobs/622226547

>       if (is_lpuart32(dev))
>               return _lpuart32_serial_init(dev);
>       else




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de

Attachment: pgpz70uSlDEI2.pgp
Description: OpenPGP digital signature

Reply via email to