> -----Original Message-----
> From: thor.tha...@linux.intel.com <thor.tha...@linux.intel.com>
> Sent: Saturday, December 7, 2019 3:48 AM
> To: ma...@denx.de; simon.k.r.goldschm...@gmail.com; Tan, Ley Foon
> <ley.foon....@intel.com>
> Cc: albert.u.b...@aribaud.net; Ang, Chee Hong
> <chee.hong....@intel.com>; Chee, Tien Fong <tien.fong.c...@intel.com>;
> u-boot@lists.denx.de; Thor Thayer <thor.tha...@linux.intel.com>
> Subject: [PATCHv2 2/2] ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC
> Access
>
> From: Thor Thayer <thor.tha...@linux.intel.com>
>
> The ECC registers in the SDRAM HMC Adapter should always be accessible
> (both when ECC is enabled and disabled).
> Currently, the registers are accessible only when ECC is enabled.
>
> The ECC Enabled bit is used to determine the status of ECC by later OSes so
> always allow access.
>
> Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com>
Reviewed-by: Ley Foon Tan <ley.foon....@intel.com>
> ---
> v2 New Patch. Rebase patch on top of pending patchset
> [PATCH v8 00/19] Add Intel Agilex SoC support
> https://patchwork.ozlabs.org/cover/1201373/
> ---
> drivers/ddr/altera/sdram_agilex.c | 6 +++---
> drivers/ddr/altera/sdram_s10.c | 6 +++---
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/ddr/altera/sdram_agilex.c
> b/drivers/ddr/altera/sdram_agilex.c
> index cc7679a6e4c1..0cbcd1405607 100644
> --- a/drivers/ddr/altera/sdram_agilex.c
> +++ b/drivers/ddr/altera/sdram_agilex.c
> @@ -143,9 +143,6 @@ int sdram_mmr_init_full(struct udevice *dev)
> setbits_le32(plat->hmc + ERRINTEN,
> DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK);
>
> - /* Enable non-secure writes to HMC Adapter for SDRAM ECC
> */
> - writel(FW_HMC_ADAPTOR_MPU_MASK,
> FW_HMC_ADAPTOR_REG_ADDR);
> -
> if (!cpu_has_been_warmreset())
> sdram_init_ecc_bits(&bd);
> } else {
> @@ -158,6 +155,9 @@ int sdram_mmr_init_full(struct udevice *dev)
> DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
> }
>
> + /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC
> */
> + writel(FW_HMC_ADAPTOR_MPU_MASK,
> FW_HMC_ADAPTOR_REG_ADDR);
> +
> sdram_size_check(&bd);
>
> priv->info.base = bd.bi_dram[0].start; diff --git
> a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index
> a7bf82e4e5ce..2b8889260f9f 100644
> --- a/drivers/ddr/altera/sdram_s10.c
> +++ b/drivers/ddr/altera/sdram_s10.c
> @@ -306,9 +306,6 @@ int sdram_mmr_init_full(struct udevice *dev)
> DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
> hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK,
> ERRINTENS);
>
> - /* Enable non-secure writes to HMC Adapter for SDRAM ECC
> */
> - writel(FW_HMC_ADAPTOR_MPU_MASK,
> FW_HMC_ADAPTOR_REG_ADDR);
> -
> /* Initialize memory content if not from warm reset */
> if (!cpu_has_been_warmreset())
> sdram_init_ecc_bits(&bd);
> @@ -322,6 +319,9 @@ int sdram_mmr_init_full(struct udevice *dev)
> DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
> }
>
> + /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC
> */
> + writel(FW_HMC_ADAPTOR_MPU_MASK,
> FW_HMC_ADAPTOR_REG_ADDR);
> +
> sdram_size_check(&bd);
>
> priv->info.base = bd.bi_dram[0].start;
> --
> 2.7.4
