пн, 23 груд. 2019 о 22:12 Ryder Lee <ryder....@mediatek.com> пише:
> On Mon, 2019-12-23 at 17:28 +0800, mingming lee wrote: > > Add support for MediaTek MT8512 SoC. This include the file > > that will initialize the SoC after boot and its device tree. > > > > Signed-off-by: mingming lee <mingming....@mediatek.com> > > --- > > arch/arm/dts/mt8512.dtsi | 115 ++++++++++++++++++ > > arch/arm/mach-mediatek/Kconfig | 15 +++ > > arch/arm/mach-mediatek/Makefile | 1 + > > arch/arm/mach-mediatek/mt8512/Makefile | 4 + > > arch/arm/mach-mediatek/mt8512/init.c | 78 ++++++++++++ > > arch/arm/mach-mediatek/mt8512/lowlevel_init.S | 32 +++++ > > 6 files changed, 245 insertions(+) > > create mode 100644 arch/arm/dts/mt8512.dtsi > > create mode 100644 arch/arm/mach-mediatek/mt8512/Makefile > > create mode 100644 arch/arm/mach-mediatek/mt8512/init.c > > create mode 100644 arch/arm/mach-mediatek/mt8512/lowlevel_init.S > > > > diff --git a/arch/arm/dts/mt8512.dtsi b/arch/arm/dts/mt8512.dtsi > > new file mode 100644 > > index 0000000000..543f068cb8 > > --- /dev/null > > +++ b/arch/arm/dts/mt8512.dtsi > > @@ -0,0 +1,115 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* > > + * Copyright (C) 2019 MediaTek Inc. > > + * Author: Mingming Lee <mingming....@mediatek.com> > > + * > > + */ > > + > > +#include <dt-bindings/clock/mt8512-clk.h> > > +#include <dt-bindings/gpio/gpio.h> > > +#include <dt-bindings/interrupt-controller/irq.h> > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > > + > > +/ { > > + compatible = "mediatek,mt8512"; > > + interrupt-parent = <&sysirq>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > Sort device nodes alphabetically. > Why alphabetically? > > > + topckgen: clock-controller@10000000 { > > + compatible = "mediatek,mt8512-topckgen"; > > + reg = <0x10000000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + topckgen_cg: clock-controller-cg@10000000 { > > + compatible = "mediatek,mt8512-topckgen-cg"; > > + reg = <0x10000000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + infracfg: clock-controller@10001000 { > > + compatible = "mediatek,mt8512-infracfg"; > > + reg = <0x10001000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + gic: interrupt-controller@0c000000 { > > + compatible = "arm,gic-v3"; > > + #interrupt-cells = <3>; > > + interrupt-parent = <&gic>; > > + interrupt-controller; > > + reg = <0xc000000 0x40000>, /* GICD */ > > + <0xc080000 0x200000>; /* GICR */ > > + interrupts = <GIC_PPI 9 > > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > > + }; > > + > > + sysirq: interrupt-controller@10200a80 { > > + compatible = "mediatek,sysirq"; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + interrupt-parent = <&gic>; > > + reg = <0x10200a80 0x50>; > > + }; > > + > > + timer0: apxgpt@10008000 { > > + compatible = "mediatek,timer"; > > + reg = <0x10008000 0x1000>; > > + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>; > > + clocks = <&topckgen CLK_TOP_SYS_26M_D2>, > > + <&topckgen CLK_TOP_CLK32K>, > > + <&infracfg CLK_INFRA_APXGPT>; > > + clock-names = "clk13m", > > + "clk32k", > > + "bus"; > > + }; > > + > > + watchdog0: watchdog@10007000 { > > + compatible = "mediatek,wdt"; > > + reg = <0x10007000 0x1000>; > > + interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_FALLING>; > > + #reset-cells = <1>; > > + status = "disabled"; > > + timeout-sec = <60>; > > + reset-on-timeout; > > + }; > > + > > + pinctrl: pinctrl@10005000 { > > + compatible = "mediatek,mt8512-pinctrl"; > > + reg = <0x10005000 0x1000>; > > + gpio: gpio-controller { > > + gpio-controller; > > + #gpio-cells = <2>; > > + }; > > + }; > > + > > + apmixedsys: clock-controller@1000c000 { > > + compatible = "mediatek,mt8512-apmixedsys"; > > + reg = <0x1000c000 0x1000>; > > + #clock-cells = <1>; > > + }; > > + > > + mmc0: mmc@11230000 { > > + compatible = "mediatek,mt8512-mmc"; > > + reg = <0x11230000 0x1000>, > > + <0x11cd0000 0x1000>; > > + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; > > + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, > > + <&infracfg CLK_INFRA_MSDC0>, > > + <&infracfg CLK_INFRA_MSDC0_SRC>; > > + clock-names = "source", "hclk", "source_cg"; > > + status = "disabled"; > > + }; > > + > > + uart0: serial@11002000 { > > + compatible = "mediatek,hsuart"; > > + reg = <0x11002000 0x1000>; > > + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>; > > + clocks = <&topckgen CLK_TOP_CLK26M>, > > + <&infracfg CLK_INFRA_UART0>; > > + clock-names = "baud", "bus"; > > + status = "disabled"; > > + }; > > + > > +}; > > diff --git a/arch/arm/mach-mediatek/Kconfig > b/arch/arm/mach-mediatek/Kconfig > > index ad453a60c1..bca88b8db8 100644 > > --- a/arch/arm/mach-mediatek/Kconfig > > +++ b/arch/arm/mach-mediatek/Kconfig > > @@ -6,6 +6,10 @@ config SYS_SOC > > config SYS_VENDOR > > default "mediatek" > > > > +config MT8512 > > + bool "MediaTek MT8512 SoC" > > + default n > > + > > choice > > prompt "MediaTek board select" > > > > @@ -29,6 +33,16 @@ config TARGET_MT7629 > > including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit > Ethernet, > > switch, USB3.0, PCIe, UART, SPI, I2C and PWM. > > > > +config TARGET_MT8512 > > + bool "MediaTek MT8512 M1 Board" > > + select ARM64 > > + select MT8512 > > + help > > + The MediaTek MT8512 is a ARM64-based SoC with a quad-core > Cortex-A53. > > + including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, > PWM, > > + Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / > Bluetooth combo > > + chip and several DDR3 and DDR4 options. > > + > > config TARGET_MT8516 > > bool "MediaTek MT8516 SoC" > > select ARM64 > > @@ -51,6 +65,7 @@ endchoice > > > > source "board/mediatek/mt7623/Kconfig" > > source "board/mediatek/mt7629/Kconfig" > > +source "board/mediatek/mt8512/Kconfig" > > source "board/mediatek/mt8518/Kconfig" > > source "board/mediatek/pumpkin/Kconfig" > > > > diff --git a/arch/arm/mach-mediatek/Makefile > b/arch/arm/mach-mediatek/Makefile > > index b9b2355e03..6129ac88ab 100644 > > --- a/arch/arm/mach-mediatek/Makefile > > +++ b/arch/arm/mach-mediatek/Makefile > > @@ -3,6 +3,7 @@ > > obj-y += cpu.o > > obj-$(CONFIG_SPL_BUILD) += spl.o > > > > +obj-$(CONFIG_MT8512) += mt8512/ > > obj-$(CONFIG_TARGET_MT7623) += mt7623/ > > obj-$(CONFIG_TARGET_MT7629) += mt7629/ > > obj-$(CONFIG_TARGET_MT8516) += mt8516/ > > diff --git a/arch/arm/mach-mediatek/mt8512/Makefile > b/arch/arm/mach-mediatek/mt8512/Makefile > > new file mode 100644 > > index 0000000000..007eb4a367 > > --- /dev/null > > +++ b/arch/arm/mach-mediatek/mt8512/Makefile > > @@ -0,0 +1,4 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > + > > +obj-y += init.o > > +obj-y += lowlevel_init.o > > diff --git a/arch/arm/mach-mediatek/mt8512/init.c > b/arch/arm/mach-mediatek/mt8512/init.c > > new file mode 100644 > > index 0000000000..a38b5d12d9 > > --- /dev/null > > +++ b/arch/arm/mach-mediatek/mt8512/init.c > > @@ -0,0 +1,78 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Configuration for MediaTek MT8512 SoC > > + * > > + * Copyright (C) 2019 MediaTek Inc. > > + * Author: Mingming Lee <mingming....@mediatek.com> > > + */ > > + > > +#include <clk.h> > > +#include <common.h> > > +#include <dm.h> > > +#include <fdtdec.h> > > +#include <ram.h> > > +#include <wdt.h> > > +#include <asm/arch/misc.h> > > +#include <asm/armv8/mmu.h> > > +#include <asm/sections.h> > > +#include <dm/uclass.h> > > +#include <dt-bindings/clock/mt8512-clk.h> > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +int dram_init(void) > > +{ > > + return fdtdec_setup_mem_size_base(); > > +} > > + > > +phys_size_t get_effective_memsize(void) > > +{ > > + /* limit stack below tee reserve memory */ > > + return gd->ram_size - 6 * SZ_1M; > > +} > > + > > +int dram_init_banksize(void) > > +{ > > + gd->bd->bi_dram[0].start = gd->ram_base; > > + gd->bd->bi_dram[0].size = get_effective_memsize(); > > + > > + return 0; > > +} > > + > > +void reset_cpu(ulong addr) > > +{ > > + struct udevice *watchdog_dev = NULL; > > + > > + if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) > > + if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) > > + psci_system_reset(); > > + > > + wdt_expire_now(watchdog_dev, 0); > > +} > > + > > +int print_cpuinfo(void) > > +{ > > + debug("CPU: MediaTek MT8512\n"); > > + return 0; > > +} > > + > > +static struct mm_region mt8512_mem_map[] = { > > + { > > + /* DDR */ > > + .virt = 0x40000000UL, > > + .phys = 0x40000000UL, > > + .size = 0x40000000UL, > > + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | > PTE_BLOCK_OUTER_SHARE, > > + }, { > > + .virt = 0x00000000UL, > > + .phys = 0x00000000UL, > > + .size = 0x40000000UL, > > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > > + PTE_BLOCK_NON_SHARE | > > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > > + }, { > > + 0, > > + } > > +}; > > + > > +struct mm_region *mem_map = mt8512_mem_map; > > diff --git a/arch/arm/mach-mediatek/mt8512/lowlevel_init.S > b/arch/arm/mach-mediatek/mt8512/lowlevel_init.S > > new file mode 100644 > > index 0000000000..ad392120f4 > > --- /dev/null > > +++ b/arch/arm/mach-mediatek/mt8512/lowlevel_init.S > > @@ -0,0 +1,32 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright (C) 2019 MediaTek Inc. > > + * Author: Mingming Lee <mingming....@mediatek.com> > > + */ > > + > > +/* > > + * Switch from AArch64 EL2 to AArch32 EL2 > > + * @param inputs: > > + * x0: argument, zero > > + * x1: machine nr > > + * x2: fdt address > > + * x3: input argument > > + * x4: kernel entry point > > + * @param outputs for secure firmware: > > + * x0: function id > > + * x1: kernel entry point > > + * x2: machine nr > > + * x3: fdt address > > +*/ > > +.global armv8_el2_to_aarch32 > > +armv8_el2_to_aarch32: > > + mov x3, x2 > > + mov x2, x1 > > + mov x1, x4 > > + mov x4, #0 > > + /* Define in src\bsp\trustzone\atf\v1.2\ */ > > + /* mt8xxx\plat\mediatek\common\sip_svc.h */ > > + /* MTK_SIP_KERNEL_BOOT_AARCH64 for U-BOOT-64 to KERNEL*/ > > + ldr x0, =0xC2000200 > > + SMC #0 > > + ret > > -- WBW ------- Rybalko Oleksandr <r...@ddteam.net>