[PATCH 12/22] ddr: imx8m: Add DRAM PLL to generate 1000Mhz output

[Peng Fan]

We will generate DRAM 4000MT/s as default for i.MX8MP.
So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller.

Signed-off-by: Peng Fan <peng....@nxp.com>
---
 drivers/ddr/imx/imx8m/ddrphy_utils.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c 
b/drivers/ddr/imx/imx8m/ddrphy_utils.c
index e60503309e..7b4ab7c77a 100644
--- a/drivers/ddr/imx/imx8m/ddrphy_utils.c
+++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c
@@ -106,6 +106,10 @@ void wait_ddrphy_training_complete(void)
 void ddrphy_init_set_dfi_clk(unsigned int drate)
 {
        switch (drate) {
+       case 4000:
+               dram_pll_init(MHZ(1000));
+               dram_disable_bypass();
+               break;
        case 3200:
                dram_pll_init(MHZ(800));
                dram_disable_bypass();
-- 
2.16.4