[PATCH 8/8] ARM: dts: imx6qdli-icore: Add fec phy-handle

[Jagan Teki]

From: Michael Trimarchi <mich...@amarulasolutions.com>

LAN8720 needs a reset of every clock enable. The reset needs
to be done at device level, due the flag PHY_RST_AFTER_CLK_EN.

So, add phy-handle by creating mdio child node inside fec.
This will eventually move the phy-reset-gpio which is defined
in fec node.

Signed-off-by: Michael Trimarchi <mich...@amarulasolutions.com>
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
 arch/arm/dts/imx6qdl-icore.dtsi | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/imx6qdl-icore.dtsi b/arch/arm/dts/imx6qdl-icore.dtsi
index 7814f1ef08..756f3a9f1b 100644
--- a/arch/arm/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/dts/imx6qdl-icore.dtsi
@@ -150,10 +150,23 @@
 &fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
-       phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
        clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, 
<&rmii_clk>;
        phy-mode = "rmii";
+       phy-handle = <&eth_phy>;
        status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               eth_phy: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0>;
+                       reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+                       reset-assert-us = <4000>;
+                       reset-deassert-us = <4000>;
+               };
+       };
 };
 
 &gpmi {
-- 
2.18.0.321.gffc6fa0e3