from
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git/
tag "ux500-armsoc-v5.6-2"
commit 224bf0fe7292 ("ARM: dts: ux500: samsung-golden: Add Bluetooth")
(queued for merge in Linux 5.6)
Signed-off-by: Stephan Gerhold <step...@gerhold.net>
---
I ignored all the checkpatch complaints in this patch,
since the files are copied without modification from the Linux kernel.
I will check if it makes sense to submit a patch to fix some of them...
(In particular the large amount of "WARNING: please, no space before tabs"
in one of the includes...)
arch/arm/dts/ste-ab8500.dtsi | 328 ++++++
arch/arm/dts/ste-ab8505.dtsi | 275 +++++
arch/arm/dts/ste-dbx5x0.dtsi | 1144 ++++++++++++++++++++
include/dt-bindings/arm/ux500_pm_domains.h | 15 +
include/dt-bindings/clock/ste-ab8500.h | 12 +
include/dt-bindings/mfd/dbx500-prcmu.h | 84 ++
6 files changed, 1858 insertions(+)
create mode 100644 arch/arm/dts/ste-ab8500.dtsi
create mode 100644 arch/arm/dts/ste-ab8505.dtsi
create mode 100644 arch/arm/dts/ste-dbx5x0.dtsi
create mode 100644 include/dt-bindings/arm/ux500_pm_domains.h
create mode 100644 include/dt-bindings/clock/ste-ab8500.h
create mode 100644 include/dt-bindings/mfd/dbx500-prcmu.h
diff --git a/arch/arm/dts/ste-ab8500.dtsi b/arch/arm/dts/ste-ab8500.dtsi
new file mode 100644
index 0000000000..14d4d8617d
--- /dev/null
+++ b/arch/arm/dts/ste-ab8500.dtsi
@@ -0,0 +1,328 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2012 Linaro Ltd
+ */
+
+#include <dt-bindings/clock/ste-ab8500.h>
+
+/ {
+ /* Essential housekeeping hardware monitors */
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&gpadc 0x02>, /* Battery temperature */
+ <&gpadc 0x03>, /* Main charger voltage */
+ <&gpadc 0x08>, /* Main battery voltage */
+ <&gpadc 0x09>, /* VBUS */
+ <&gpadc 0x0a>, /* Main charger current */
+ <&gpadc 0x0b>, /* USB charger current */
+ <&gpadc 0x0c>, /* Backup battery voltage */
+ <&gpadc 0x0d>, /* Die temperature */
+ <&gpadc 0x12>; /* Crystal temperature */
+ };
+
+ soc {
+ prcmu@80157000 {
+ ab8500 {
+ compatible = "stericsson,ab8500";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ab8500_clock: clock-controller {
+ compatible = "stericsson,ab8500-clk";
+ #clock-cells = <1>;
+ };
+
+ ab8500_gpio: ab8500-gpio {
+ compatible = "stericsson,ab8500-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ ab8500-rtc {
+ compatible = "stericsson,ab8500-rtc";
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH
+ 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "60S", "ALARM";
+ };
+
+ gpadc: ab8500-gpadc {
+ compatible = "stericsson,ab8500-gpadc";
+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH
+ 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "HW_CONV_END",
"SW_CONV_END";
+ vddadc-supply = <&ab8500_ldo_tvout_reg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ /* GPADC channels */
+ bat_ctrl: channel@01 {
+ reg = <0x01>;
+ };
+ btemp_ball: channel@02 {
+ reg = <0x02>;
+ };
+ main_charger_v: channel@03 {
+ reg = <0x03>;
+ };
+ acc_detect1: channel@04 {
+ reg = <0x04>;
+ };
+ acc_detect2: channel@05 {
+ reg = <0x05>;
+ };
+ adc_aux1: channel@06 {
+ reg = <0x06>;
+ };
+ adc_aux2: channel@07 {
+ reg = <0x07>;
+ };
+ main_batt_v: channel@08 {
+ reg = <0x08>;
+ };
+ vbus_v: channel@09 {
+ reg = <0x09>;
+ };
+ main_charger_c: channel@0a {
+ reg = <0x0a>;
+ };
+ usb_charger_c: channel@0b {
+ reg = <0x0b>;
+ };
+ bk_bat_v: channel@0c {
+ reg = <0x0c>;
+ };
+ die_temp: channel@0d {
+ reg = <0x0d>;
+ };
+ usb_id: channel@0e {
+ reg = <0x0e>;
+ };
+ xtal_temp: channel@12 {
+ reg = <0x12>;
+ };
+ vbat_true_meas: channel@13 {
+ reg = <0x13>;
+ };
+ bat_ctrl_and_ibat: channel@1c {
+ reg = <0x1c>;
+ };
+ vbat_meas_and_ibat: channel@1d {
+ reg = <0x1d>;
+ };
+ vbat_true_meas_and_ibat: channel@1e {
+ reg = <0x1e>;
+ };
+ bat_temp_and_ibat: channel@1f {
+ reg = <0x1f>;
+ };
+ };
+
+ ab8500_temp {
+ compatible = "stericsson,abx500-temp";
+ io-channels = <&gpadc 0x06>,
+ <&gpadc 0x07>;
+ io-channel-name = "aux1", "aux2";
+ };
+
+ ab8500_battery: ab8500_battery {
+ stericsson,battery-type = "LIPO";
+ thermistor-on-batctrl;
+ };
+
+ ab8500_fg {
+ compatible = "stericsson,ab8500-fg";
+ battery = <&ab8500_battery>;
+ io-channels = <&gpadc 0x08>;
+ io-channel-name = "main_bat_v";
+ };
+
+ ab8500_btemp {
+ compatible = "stericsson,ab8500-btemp";
+ battery = <&ab8500_battery>;
+ io-channels = <&gpadc 0x02>,
+ <&gpadc 0x01>;
+ io-channel-name = "btemp_ball",
+ "bat_ctrl";
+ };
+
+ ab8500_charger {
+ compatible =
"stericsson,ab8500-charger";
+ battery = <&ab8500_battery>;
+ vddadc-supply =
<&ab8500_ldo_tvout_reg>;
+ io-channels = <&gpadc 0x03>,
+ <&gpadc 0x0a>,
+ <&gpadc 0x09>,
+ <&gpadc 0x0b>;
+ io-channel-name = "main_charger_v",
+ "main_charger_c",
+ "vbus_v",
+ "usb_charger_c";
+ };
+
+ ab8500_chargalg {
+ compatible =
"stericsson,ab8500-chargalg";
+ battery = <&ab8500_battery>;
+ };
+
+ ab8500_usb {
+ compatible = "stericsson,ab8500-usb";
+ interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
+ 96 IRQ_TYPE_LEVEL_HIGH
+ 14 IRQ_TYPE_LEVEL_HIGH
+ 15 IRQ_TYPE_LEVEL_HIGH
+ 79 IRQ_TYPE_LEVEL_HIGH
+ 74 IRQ_TYPE_LEVEL_HIGH
+ 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ID_WAKEUP_R",
+ "ID_WAKEUP_F",
+ "VBUS_DET_F",
+ "VBUS_DET_R",
+ "USB_LINK_STATUS",
+ "USB_ADP_PROBE_PLUG",
+
"USB_ADP_PROBE_UNPLUG";
+ vddulpivio18-supply =
<&ab8500_ldo_intcore_reg>;
+ v-ape-supply = <&db8500_vape_reg>;
+ musb_1v8-supply = <&db8500_vsmps2_reg>;
+ clocks = <&prcmu_clk PRCMU_SYSCLK>;
+ clock-names = "sysclk";
+ };
+
+ ab8500-ponkey {
+ compatible =
"stericsson,ab8500-poweron-key";
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH
+ 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ONKEY_DBF",
"ONKEY_DBR";
+ };
+
+ ab8500-sysctrl {
+ compatible =
"stericsson,ab8500-sysctrl";
+ };
+
+ ab8500-pwm {
+ compatible = "stericsson,ab8500-pwm";
+ clocks = <&ab8500_clock
AB8500_SYSCLK_INT>;
+ clock-names = "intclk";
+ };
+
+ ab8500-debugfs {
+ compatible = "stericsson,ab8500-debug";
+ };
+
+ codec: ab8500-codec {
+ compatible = "stericsson,ab8500-codec";
+
+ V-AUD-supply = <&ab8500_ldo_audio_reg>;
+ V-AMIC1-supply =
<&ab8500_ldo_anamic1_reg>;
+ V-AMIC2-supply =
<&ab8500_ldo_anamic2_reg>;
+ V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
+
+ clocks = <&ab8500_clock
AB8500_SYSCLK_AUDIO>;
+ clock-names = "audioclk";
+
+ stericsson,earpeice-cmv = <950>; /*
Units in mV. */
+ };
+
+ ext_regulators: ab8500-ext-regulators {
+ compatible =
"stericsson,ab8500-ext-regulator";
+
+ ab8500_ext1_reg: ab8500_ext1 {
+ regulator-min-microvolt =
<1800000>;
+ regulator-max-microvolt =
<1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ab8500_ext2_reg: ab8500_ext2 {
+ regulator-min-microvolt =
<1360000>;
+ regulator-max-microvolt =
<1360000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ab8500_ext3_reg: ab8500_ext3 {
+ regulator-min-microvolt =
<3400000>;
+ regulator-max-microvolt =
<3400000>;
+ regulator-boot-on;
+ };
+ };
+
+ ab8500-regulators {
+ compatible =
"stericsson,ab8500-regulator";
+ vin-supply = <&ab8500_ext3_reg>;
+
+ // supplies to the display/camera
+ ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
+ regulator-min-microvolt =
<2500000>;
+ regulator-max-microvolt =
<2900000>;
+ regulator-boot-on;
+ /* BUG: If turned off MMC will
be affected. */
+ regulator-always-on;
+ };
+
+ // supplies to the on-board eMMC
+ ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
+ regulator-min-microvolt =
<1100000>;
+ regulator-max-microvolt =
<3300000>;
+ };
+
+ // supply for VAUX3; SDcard slots
+ ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
+ regulator-min-microvolt =
<1100000>;
+ regulator-max-microvolt =
<3300000>;
+ };
+
+ // supply for v-intcore12; VINTCORE12
LDO
+ ab8500_ldo_intcore_reg:
ab8500_ldo_intcore {
+ };
+
+ // supply for tvout; gpadc; TVOUT LDO
+ ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
+ };
+
+ // supply for ab8500-vaudio; VAUDIO LDO
+ ab8500_ldo_audio_reg: ab8500_ldo_audio {
+ };
+
+ // supply for v-anamic1 VAMIC1 LDO
+ ab8500_ldo_anamic1_reg:
ab8500_ldo_anamic1 {
+ };
+
+ // supply for v-amic2; VAMIC2 LDO;
reuse constants for AMIC1
+ ab8500_ldo_anamic2_reg:
ab8500_ldo_anamic2 {
+ };
+
+ // supply for v-dmic; VDMIC LDO
+ ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
+ };
+
+ // supply for U8500 CSI/DSI; VANA LDO
+ ab8500_ldo_ana_reg: ab8500_ldo_ana {
+ };
+ };
+ };
+ };
+
+ sound {
+ stericsson,audio-codec = <&codec>;
+ clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock
AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>;
+ clock-names = "sysclk", "ulpclk", "intclk";
+ };
+
+ mcde@a0350000 {
+ vana-supply = <&ab8500_ldo_ana_reg>;
+
+ dsi@a0351000 {
+ vana-supply = <&ab8500_ldo_ana_reg>;
+ };
+ dsi@a0352000 {
+ vana-supply = <&ab8500_ldo_ana_reg>;
+ };
+ dsi@a0353000 {
+ vana-supply = <&ab8500_ldo_ana_reg>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/ste-ab8505.dtsi b/arch/arm/dts/ste-ab8505.dtsi
new file mode 100644
index 0000000000..c72aa250bf
--- /dev/null
+++ b/arch/arm/dts/ste-ab8505.dtsi
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2012 Linaro Ltd
+ */
+
+#include <dt-bindings/clock/ste-ab8500.h>
+
+/ {
+ /* Essential housekeeping hardware monitors */
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&gpadc 0x02>, /* Battery temperature */
+ <&gpadc 0x08>, /* Main battery voltage */
+ <&gpadc 0x09>, /* VBUS */
+ <&gpadc 0x0b>, /* Charger current */
+ <&gpadc 0x0c>; /* Backup battery voltage */
+ };
+
+ soc {
+ prcmu@80157000 {
+ ab8505 {
+ compatible = "stericsson,ab8505";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ab8500_clock: clock-controller {
+ compatible = "stericsson,ab8500-clk";
+ #clock-cells = <1>;
+ };
+
+ ab8505_gpio: ab8505-gpio {
+ compatible = "stericsson,ab8505-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ ab8500-rtc {
+ compatible = "stericsson,ab8500-rtc";
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH
+ 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "60S", "ALARM";
+ };
+
+ gpadc: ab8500-gpadc {
+ compatible = "stericsson,ab8500-gpadc";
+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH
+ 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "HW_CONV_END",
"SW_CONV_END";
+ vddadc-supply = <&ab8500_ldo_adc_reg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ /* GPADC channels */
+ bat_ctrl: channel@01 {
+ reg = <0x01>;
+ };
+ btemp_ball: channel@02 {
+ reg = <0x02>;
+ };
+ acc_detect1: channel@04 {
+ reg = <0x04>;
+ };
+ acc_detect2: channel@05 {
+ reg = <0x05>;
+ };
+ adc_aux1: channel@06 {
+ reg = <0x06>;
+ };
+ adc_aux2: channel@07 {
+ reg = <0x07>;
+ };
+ main_batt_v: channel@08 {
+ reg = <0x08>;
+ };
+ vbus_v: channel@09 {
+ reg = <0x09>;
+ };
+ charger_c: channel@0b {
+ reg = <0x0b>;
+ };
+ bk_bat_v: channel@0c {
+ reg = <0x0c>;
+ };
+ usb_id: channel@0e {
+ reg = <0x0e>;
+ };
+ };
+
+ ab8500_battery: ab8500_battery {
+ status = "disabled";
+ thermistor-on-batctrl;
+ };
+
+ ab8500_fg {
+ status = "disabled";
+ compatible = "stericsson,ab8500-fg";
+ battery = <&ab8500_battery>;
+ io-channels = <&gpadc 0x08>;
+ io-channel-name = "main_bat_v";
+ };
+
+ ab8500_btemp {
+ status = "disabled";
+ compatible = "stericsson,ab8500-btemp";
+ battery = <&ab8500_battery>;
+ io-channels = <&gpadc 0x02>,
+ <&gpadc 0x01>;
+ io-channel-name = "btemp_ball",
+ "bat_ctrl";
+ };
+
+ ab8500_charger {
+ status = "disabled";
+ compatible =
"stericsson,ab8500-charger";
+ battery = <&ab8500_battery>;
+ vddadc-supply = <&ab8500_ldo_adc_reg>;
+ io-channels = <&gpadc 0x09>,
+ <&gpadc 0x0b>;
+ io-channel-name = "vbus_v",
+ "usb_charger_c";
+ };
+
+ ab8500_chargalg {
+ status = "disabled";
+ compatible =
"stericsson,ab8500-chargalg";
+ battery = <&ab8500_battery>;
+ };
+
+ ab8500_usb: ab8500_usb {
+ compatible = "stericsson,ab8500-usb";
+ interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
+ 96 IRQ_TYPE_LEVEL_HIGH
+ 14 IRQ_TYPE_LEVEL_HIGH
+ 15 IRQ_TYPE_LEVEL_HIGH
+ 79 IRQ_TYPE_LEVEL_HIGH
+ 74 IRQ_TYPE_LEVEL_HIGH
+ 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ID_WAKEUP_R",
+ "ID_WAKEUP_F",
+ "VBUS_DET_F",
+ "VBUS_DET_R",
+ "USB_LINK_STATUS",
+ "USB_ADP_PROBE_PLUG",
+
"USB_ADP_PROBE_UNPLUG";
+ vddulpivio18-supply =
<&ab8500_ldo_intcore_reg>;
+ v-ape-supply = <&db8500_vape_reg>;
+ musb_1v8-supply = <&db8500_vsmps2_reg>;
+ clocks = <&prcmu_clk PRCMU_SYSCLK>;
+ clock-names = "sysclk";
+ };
+
+ ab8500-ponkey {
+ compatible =
"stericsson,ab8500-poweron-key";
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH
+ 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ONKEY_DBF",
"ONKEY_DBR";
+ };
+
+ ab8500-sysctrl {
+ compatible =
"stericsson,ab8500-sysctrl";
+ };
+
+ ab8500-pwm {
+ compatible = "stericsson,ab8500-pwm";
+ clocks = <&ab8500_clock
AB8500_SYSCLK_INT>;
+ clock-names = "intclk";
+ };
+
+ ab8500-debugfs {
+ compatible = "stericsson,ab8500-debug";
+ };
+
+ codec: ab8500-codec {
+ compatible = "stericsson,ab8500-codec";
+
+ V-AUD-supply = <&ab8500_ldo_audio_reg>;
+ V-AMIC1-supply =
<&ab8500_ldo_anamic1_reg>;
+ V-AMIC2-supply =
<&ab8500_ldo_anamic2_reg>;
+
+ clocks = <&ab8500_clock
AB8500_SYSCLK_AUDIO>;
+ clock-names = "audioclk";
+
+ stericsson,earpeice-cmv = <950>; /*
Units in mV. */
+ };
+
+ ab8505-regulators {
+ compatible =
"stericsson,ab8505-regulator";
+
+ ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
+ regulator-min-microvolt =
<2800000>;
+ regulator-max-microvolt =
<3300000>;
+ };
+
+ ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
+ regulator-min-microvolt =
<1100000>;
+ regulator-max-microvolt =
<3300000>;
+ };
+
+ ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
+ regulator-min-microvolt =
<1100000>;
+ regulator-max-microvolt =
<3300000>;
+ };
+
+ ab8500_ldo_aux4_reg: ab8500_ldo_aux4 {
+ regulator-min-microvolt =
<1100000>;
+ regulator-max-microvolt =
<3300000>;
+ };
+
+ ab8500_ldo_aux5_reg: ab8500_ldo_aux5 {
+ regulator-min-microvolt =
<1050000>;
+ regulator-max-microvolt =
<2790000>;
+ };
+
+ ab8500_ldo_aux6_reg: ab8500_ldo_aux6 {
+ regulator-min-microvolt =
<1050000>;
+ regulator-max-microvolt =
<2790000>;
+ };
+
+ // supply for v-intcore12; VINTCORE12
LDO
+ ab8500_ldo_intcore_reg:
ab8500_ldo_intcore {
+ regulator-min-microvolt =
<1250000>;
+ regulator-max-microvolt =
<1350000>;
+ };
+
+ // supply for gpadc; ADC LDO
+ ab8500_ldo_adc_reg: ab8500_ldo_adc {
+ };
+
+ // supply for ab8500-vaudio; VAUDIO LDO
+ ab8500_ldo_audio_reg: ab8500_ldo_audio {
+ };
+
+ // supply for v-anamic1 VAMIC1 LDO
+ ab8500_ldo_anamic1_reg:
ab8500_ldo_anamic1 {
+ };
+
+ // supply for v-amic2; VAMIC2 LDO;
reuse constants for AMIC1
+ ab8500_ldo_anamic2_reg:
ab8500_ldo_anamic2 {
+ };
+
+ // supply for v-aux8; VAUX8 LDO
+ ab8500_ldo_aux8_reg: ab8500_ldo_aux8 {
+ };
+
+ // supply for U8500 CSI/DSI; VANA LDO
+ ab8500_ldo_ana_reg: ab8500_ldo_ana {
+ };
+ };
+ };
+ };
+
+ sound {
+ stericsson,audio-codec = <&codec>;
+ clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock
AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>;
+ clock-names = "sysclk", "ulpclk", "intclk";
+ };
+
+ mcde@a0350000 {
+ vana-supply = <&ab8500_ldo_ana_reg>;
+
+ dsi@a0351000 {
+ vana-supply = <&ab8500_ldo_ana_reg>;
+ };
+ dsi@a0352000 {
+ vana-supply = <&ab8500_ldo_ana_reg>;
+ };
+ dsi@a0353000 {
+ vana-supply = <&ab8500_ldo_ana_reg>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/ste-dbx5x0.dtsi b/arch/arm/dts/ste-dbx5x0.dtsi
new file mode 100644
index 0000000000..6671f74c9f
--- /dev/null
+++ b/arch/arm/dts/ste-dbx5x0.dtsi
@@ -0,0 +1,1144 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2012 Linaro Ltd
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mfd/dbx500-prcmu.h>
+#include <dt-bindings/arm/ux500_pm_domains.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* This stablilizes the device enumeration */
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ };
+
+ chosen {
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "ste,dbx500-smp";
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+ core1 {
+ cpu = <&CPU1>;
+ };
+ };
+ };
+ CPU0: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0x300>;
+ clocks = <&prcmu_clk PRCMU_ARMSS>;
+ clock-names = "cpu";
+ clock-latency = <20000>;
+ #cooling-cells = <2>;
+ };
+ CPU1: cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0x301>;
+ };
+ };
+
+ thermal-zones {
+ /*
+ * Thermal zone for the SoC, using the thermal sensor in the
+ * PRCMU for temperature and the cpufreq driver for passive
+ * cooling.
+ */
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <250>;
+ /*
+ * This sensor fires interrupts to update the thermal
+ * zone, so no polling is needed.
+ */
+ polling-delay = <0>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu-crit {
+ temperature = <85000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ trip = <&cpu_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
+ contribution = <100>;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "stericsson,db8500", "simple-bus";
+ interrupt-parent = <&intc>;
+ ranges;
+
+ ptm@801ae000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x801ae000 0x1000>;
+
+ clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk
PRCMU_APEATCLK>;
+ clock-names = "apb_pclk", "atclk";
+ cpu = <&CPU0>;
+ out-ports {
+ port {
+ ptm0_out_port: endpoint {
+ remote-endpoint =
<&funnel_in_port0>;
+ };
+ };
+ };
+ };
+
+ ptm@801af000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x801af000 0x1000>;
+
+ clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk
PRCMU_APEATCLK>;
+ clock-names = "apb_pclk", "atclk";
+ cpu = <&CPU1>;
+ out-ports {
+ port {
+ ptm1_out_port: endpoint {
+ remote-endpoint =
<&funnel_in_port1>;
+ };
+ };
+ };
+ };
+
+ funnel@801a6000 {
+ compatible = "arm,coresight-dynamic-funnel",
"arm,primecell";
+ reg = <0x801a6000 0x1000>;
+
+ clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk
PRCMU_APEATCLK>;
+ clock-names = "apb_pclk", "atclk";
+ out-ports {
+ port {
+ funnel_out_port: endpoint {
+ remote-endpoint =
+ <&replicator_in_port0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_in_port0: endpoint {
+ remote-endpoint =
<&ptm0_out_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_in_port1: endpoint {
+ remote-endpoint =
<&ptm1_out_port>;
+ };
+ };
+ };
+ };
+
+ replicator {
+ compatible = "arm,coresight-static-replicator";
+ clocks = <&prcmu_clk PRCMU_APEATCLK>;
+ clock-names = "atclk";
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint =
<&tpiu_in_port>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ replicator_out_port1: endpoint {
+ remote-endpoint =
<&etb_in_port>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ replicator_in_port0: endpoint {
+ remote-endpoint =
<&funnel_out_port>;
+ };
+ };
+ };
+ };
+
+ tpiu@80190000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0x80190000 0x1000>;
+
+ clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk
PRCMU_APEATCLK>;
+ clock-names = "apb_pclk", "atclk";
+ in-ports {
+ port {
+ tpiu_in_port: endpoint {
+ remote-endpoint =
<&replicator_out_port0>;
+ };
+ };
+ };
+ };
+
+ etb@801a4000 {
+ compatible = "arm,coresight-etb10", "arm,primecell";
+ reg = <0x801a4000 0x1000>;
+
+ clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk
PRCMU_APEATCLK>;
+ clock-names = "apb_pclk", "atclk";
+ in-ports {
+ port {
+ etb_in_port: endpoint {
+ remote-endpoint =
<&replicator_out_port1>;
+ };
+ };
+ };
+ };
+
+ intc: interrupt-controller@a0411000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ interrupt-controller;
+ reg = <0xa0411000 0x1000>,
+ <0xa0410100 0x100>;
+ };
+
+ scu@a0410000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xa0410000 0x100>;
+ };
+
+ /*
+ * The backup RAM is used for retention during sleep
+ * and various things like spin tables
+ */
+ backupram@80150000 {
+ compatible = "ste,dbx500-backupram";
+ reg = <0x80150000 0x2000>;
+ };
+
+ L2: l2-cache {
+ compatible = "arm,pl310-cache";
+ reg = <0xa0412000 0x1000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pm_domains: pm_domains0 {
+ compatible = "stericsson,ux500-pm-domains";
+ #power-domain-cells = <1>;
+ };
+
+ clocks {
+ compatible = "stericsson,u8500-clks";
+ /*
+ * Registers for the CLKRST block on peripheral
+ * groups 1, 2, 3, 5, 6,
+ */
+ reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
+ <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
+ <0xa03cf000 0x1000>;
+
+ prcmu_clk: prcmu-clock {
+ #clock-cells = <1>;
+ };
+
+ prcc_pclk: prcc-periph-clock {
+ #clock-cells = <2>;
+ };
+
+ prcc_kclk: prcc-kernel-clock {
+ #clock-cells = <2>;
+ };
+
+ rtc_clk: rtc32k-clock {
+ #clock-cells = <0>;
+ };
+
+ smp_twd_clk: smp-twd-clock {
+ #clock-cells = <0>;
+ };
+ };
+
+ mtu@a03c6000 {
+ /* Nomadik System Timer */
+ compatible = "st,nomadik-mtu";
+ reg = <0xa03c6000 0x1000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
+ clock-names = "timclk", "apb_pclk";
+ };
+
+ timer@a0410600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0xa0410600 0x20>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) |
IRQ_TYPE_LEVEL_HIGH)>;
+
+ clocks = <&smp_twd_clk>;
+ };
+
+ watchdog@a0410620 {
+ compatible = "arm,cortex-a9-twd-wdt";
+ reg = <0xa0410620 0x20>;
+ interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) |
IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&smp_twd_clk>;
+ };
+
+ rtc@80154000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x80154000 0x1000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&rtc_clk>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio0: gpio@8012e000 {
+ compatible = "stericsson,db8500-gpio",
+ "st,nomadik-gpio";
+ reg = <0x8012e000 0x80>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,supports-sleepmode;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-bank = <0>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ clocks = <&prcc_pclk 1 9>;
+ };
+
+ gpio1: gpio@8012e080 {
+ compatible = "stericsson,db8500-gpio",
+ "st,nomadik-gpio";
+ reg = <0x8012e080 0x80>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,supports-sleepmode;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-bank = <1>;
+ gpio-ranges = <&pinctrl 0 32 5>;
+ clocks = <&prcc_pclk 1 9>;
+ };
+
+ gpio2: gpio@8000e000 {
+ compatible = "stericsson,db8500-gpio",
+ "st,nomadik-gpio";
+ reg = <0x8000e000 0x80>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,supports-sleepmode;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-bank = <2>;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ clocks = <&prcc_pclk 3 8>;
+ };
+
+ gpio3: gpio@8000e080 {
+ compatible = "stericsson,db8500-gpio",
+ "st,nomadik-gpio";
+ reg = <0x8000e080 0x80>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,supports-sleepmode;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-bank = <3>;
+ gpio-ranges = <&pinctrl 0 96 2>;
+ clocks = <&prcc_pclk 3 8>;
+ };
+
+ gpio4: gpio@8000e100 {
+ compatible = "stericsson,db8500-gpio",
+ "st,nomadik-gpio";
+ reg = <0x8000e100 0x80>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,supports-sleepmode;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-bank = <4>;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ clocks = <&prcc_pclk 3 8>;
+ };
+
+ gpio5: gpio@8000e180 {
+ compatible = "stericsson,db8500-gpio",
+ "st,nomadik-gpio";
+ reg = <0x8000e180 0x80>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,supports-sleepmode;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-bank = <5>;
+ gpio-ranges = <&pinctrl 0 160 12>;
+ clocks = <&prcc_pclk 3 8>;
+ };
+
+ gpio6: gpio@8011e000 {
+ compatible = "stericsson,db8500-gpio",
+ "st,nomadik-gpio";
+ reg = <0x8011e000 0x80>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,supports-sleepmode;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-bank = <6>;
+ gpio-ranges = <&pinctrl 0 192 32>;
+ clocks = <&prcc_pclk 2 11>;
+ };
+
+ gpio7: gpio@8011e080 {
+ compatible = "stericsson,db8500-gpio",
+ "st,nomadik-gpio";
+ reg = <0x8011e080 0x80>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,supports-sleepmode;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-bank = <7>;
+ gpio-ranges = <&pinctrl 0 224 7>;
+ clocks = <&prcc_pclk 2 11>;
+ };
+
+ gpio8: gpio@a03fe000 {
+ compatible = "stericsson,db8500-gpio",
+ "st,nomadik-gpio";
+ reg = <0xa03fe000 0x80>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ st,supports-sleepmode;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-bank = <8>;
+ gpio-ranges = <&pinctrl 0 256 12>;
+ clocks = <&prcc_pclk 5 1>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "stericsson,db8500-pinctrl";
+ nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>,
<&gpio3>,
+ <&gpio4>, <&gpio5>, <&gpio6>,
<&gpio7>,
+ <&gpio8>;
+ prcm = <&prcmu>;
+ };
+
+ usb_per5@a03e0000 {
+ compatible = "stericsson,db8500-musb";
+ reg = <0xa03e0000 0x10000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+
+ dr_mode = "otg";
+
+ dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
+ <&dma 38 0 0x0>, /* Logical - MemToDev */
+ <&dma 37 0 0x2>, /* Logical - DevToMem */
+ <&dma 37 0 0x0>, /* Logical - MemToDev */
+ <&dma 36 0 0x2>, /* Logical - DevToMem */
+ <&dma 36 0 0x0>, /* Logical - MemToDev */
+ <&dma 19 0 0x2>, /* Logical - DevToMem */
+ <&dma 19 0 0x0>, /* Logical - MemToDev */
+ <&dma 18 0 0x2>, /* Logical - DevToMem */
+ <&dma 18 0 0x0>, /* Logical - MemToDev */
+ <&dma 17 0 0x2>, /* Logical - DevToMem */
+ <&dma 17 0 0x0>, /* Logical - MemToDev */
+ <&dma 16 0 0x2>, /* Logical - DevToMem */
+ <&dma 16 0 0x0>, /* Logical - MemToDev */
+ <&dma 39 0 0x2>, /* Logical - DevToMem */
+ <&dma 39 0 0x0>; /* Logical - MemToDev */
+
+ dma-names = "iep_1_9", "oep_1_9",
+ "iep_2_10", "oep_2_10",
+ "iep_3_11", "oep_3_11",
+ "iep_4_12", "oep_4_12",
+ "iep_5_13", "oep_5_13",
+ "iep_6_14", "oep_6_14",
+ "iep_7_15", "oep_7_15",
+ "iep_8", "oep_8";
+
+ clocks = <&prcc_pclk 5 0>;
+ };
+
+ dma: dma-controller@801C0000 {
+ compatible = "stericsson,db8500-dma40",
"stericsson,dma40";
+ reg = <0x801C0000 0x1000 0x40010000 0x800>;
+ reg-names = "base", "lcpa";
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+
+ #dma-cells = <3>;
+ memcpy-channels = <56 57 58 59 60>;
+
+ clocks = <&prcmu_clk PRCMU_DMACLK>;
+ };
+
+ prcmu: prcmu@80157000 {
+ compatible = "stericsson,db8500-prcmu", "syscon";
+ reg = <0x80157000 0x2000>, <0x801b0000 0x8000>,
<0x801b8000 0x1000>;
+ reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ranges;
+
+ prcmu-timer-4@80157450 {
+ compatible = "stericsson,db8500-prcmu-timer-4";
+ reg = <0x80157450 0xC>;
+ };
+
+ thermal: thermal@801573c0 {
+ compatible = "stericsson,db8500-thermal";
+ reg = <0x801573c0 0x40>;
+ interrupt-parent = <&prcmu>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
+ <22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "IRQ_HOTMON_LOW",
"IRQ_HOTMON_HIGH";
+ #thermal-sensor-cells = <0>;
+ };
+
+ db8500-prcmu-regulators {
+ compatible =
"stericsson,db8500-prcmu-regulator";
+
+ // DB8500_REGULATOR_VAPE
+ db8500_vape_reg: db8500_vape {
+ regulator-always-on;
+ };
+
+ // DB8500_REGULATOR_VARM
+ db8500_varm_reg: db8500_varm {
+ };
+
+ // DB8500_REGULATOR_VMODEM
+ db8500_vmodem_reg: db8500_vmodem {
+ };
+
+ // DB8500_REGULATOR_VPLL
+ db8500_vpll_reg: db8500_vpll {
+ };
+
+ // DB8500_REGULATOR_VSMPS1
+ db8500_vsmps1_reg: db8500_vsmps1 {
+ };
+
+ // DB8500_REGULATOR_VSMPS2
+ db8500_vsmps2_reg: db8500_vsmps2 {
+ };
+
+ // DB8500_REGULATOR_VSMPS3
+ db8500_vsmps3_reg: db8500_vsmps3 {
+ };
+
+ // DB8500_REGULATOR_VRF1
+ db8500_vrf1_reg: db8500_vrf1 {
+ };
+
+ // DB8500_REGULATOR_SWITCH_SVAMMDSP
+ db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
+ };
+
+ // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
+ db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
+ };
+
+ // DB8500_REGULATOR_SWITCH_SVAPIPE
+ db8500_sva_pipe_reg: db8500_sva_pipe {
+ };
+
+ // DB8500_REGULATOR_SWITCH_SIAMMDSP
+ db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
+ };
+
+ // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
+ db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
+ };
+
+ // DB8500_REGULATOR_SWITCH_SIAPIPE
+ db8500_sia_pipe_reg: db8500_sia_pipe {
+ };
+
+ // DB8500_REGULATOR_SWITCH_SGA
+ db8500_sga_reg: db8500_sga {
+ vin-supply = <&db8500_vape_reg>;
+ };
+
+ // DB8500_REGULATOR_SWITCH_B2R2_MCDE
+ db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
+ vin-supply = <&db8500_vape_reg>;
+ };
+
+ // DB8500_REGULATOR_SWITCH_ESRAM12
+ db8500_esram12_reg: db8500_esram12 {
+ };
+
+ // DB8500_REGULATOR_SWITCH_ESRAM12RET
+ db8500_esram12_ret_reg: db8500_esram12_ret {
+ };
+
+ // DB8500_REGULATOR_SWITCH_ESRAM34
+ db8500_esram34_reg: db8500_esram34 {
+ };
+
+ // DB8500_REGULATOR_SWITCH_ESRAM34RET
+ db8500_esram34_ret_reg: db8500_esram34_ret {
+ };
+ };
+ };
+
+ i2c0: i2c@80004000 {
+ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c",
"arm,primecell";
+ reg = <0x80004000 0x1000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ v-i2c-supply = <&db8500_vape_reg>;
+
+ clock-frequency = <400000>;
+ clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
+ clock-names = "i2cclk", "apb_pclk";
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
+ };
+
+ i2c1: i2c@80122000 {
+ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c",
"arm,primecell";
+ reg = <0x80122000 0x1000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ v-i2c-supply = <&db8500_vape_reg>;
+
+ clock-frequency = <400000>;
+
+ clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
+ clock-names = "i2cclk", "apb_pclk";
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
+ };
+
+ i2c2: i2c@80128000 {
+ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c",
"arm,primecell";
+ reg = <0x80128000 0x1000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ v-i2c-supply = <&db8500_vape_reg>;
+
+ clock-frequency = <400000>;
+
+ clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
+ clock-names = "i2cclk", "apb_pclk";
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
+ };
+
+ i2c3: i2c@80110000 {
+ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c",
"arm,primecell";
+ reg = <0x80110000 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ v-i2c-supply = <&db8500_vape_reg>;
+
+ clock-frequency = <400000>;
+
+ clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
+ clock-names = "i2cclk", "apb_pclk";
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
+ };
+
+ i2c4: i2c@8012a000 {
+ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c",
"arm,primecell";
+ reg = <0x8012a000 0x1000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ v-i2c-supply = <&db8500_vape_reg>;
+
+ clock-frequency = <400000>;
+
+ clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
+ clock-names = "i2cclk", "apb_pclk";
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
+ };
+
+ ssp0: spi@80002000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x80002000 0x1000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
+ clock-names = "SSPCLK", "apb_pclk";
+ dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
+ <&dma 8 0 0x0>; /* Logical - MemToDev */
+ dma-names = "rx", "tx";
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
+ };
+
+ ssp1: spi@80003000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x80003000 0x1000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
+ clock-names = "SSPCLK", "apb_pclk";
+ dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
+ <&dma 9 0 0x0>; /* Logical - MemToDev */
+ dma-names = "rx", "tx";
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
+ };
+
+ spi0: spi@8011a000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x8011a000 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* Same clock wired to kernel and pclk */
+ clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
+ clock-names = "SSPCLK", "apb_pclk";
+ dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
+ <&dma 0 0 0x0>; /* Logical - MemToDev */
+ dma-names = "rx", "tx";
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
+ };
+
+ spi1: spi@80112000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x80112000 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* Same clock wired to kernel and pclk */
+ clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
+ clock-names = "SSPCLK", "apb_pclk";
+ dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
+ <&dma 35 0 0x0>; /* Logical - MemToDev */
+ dma-names = "rx", "tx";
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
+ };
+
+ spi2: spi@80111000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x80111000 0x1000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* Same clock wired to kernel and pclk */
+ clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
+ clock-names = "SSPCLK", "apb_pclk";
+ dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
+ <&dma 33 0 0x0>; /* Logical - MemToDev */
+ dma-names = "rx", "tx";
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
+ };
+
+ spi3: spi@80129000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x80129000 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* Same clock wired to kernel and pclk */
+ clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
+ clock-names = "SSPCLK", "apb_pclk";
+ dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
+ <&dma 40 0 0x0>; /* Logical - MemToDev */
+ dma-names = "rx", "tx";
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
+ };
+
+ serial0: uart@80120000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x80120000 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+
+ dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
+ <&dma 13 0 0x0>; /* Logical - MemToDev */
+ dma-names = "rx", "tx";
+
+ clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
+ clock-names = "uart", "apb_pclk";
+
+ status = "disabled";
+ };
+
+ serial1: uart@80121000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x80121000 0x1000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+
+ dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
+ <&dma 12 0 0x0>; /* Logical - MemToDev */
+ dma-names = "rx", "tx";
+
+ clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
+ clock-names = "uart", "apb_pclk";
+
+ status = "disabled";
+ };
+
+ serial2: uart@80007000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x80007000 0x1000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+
+ dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
+ <&dma 11 0 0x0>; /* Logical - MemToDev */
+ dma-names = "rx", "tx";
+
+ clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
+ clock-names = "uart", "apb_pclk";
+
+ status = "disabled";
+ };
+
+ sdi0_per1@80126000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ reg = <0x80126000 0x1000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+
+ dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
+ <&dma 29 0 0x0>; /* Logical - MemToDev */
+ dma-names = "rx", "tx";
+
+ clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
+ clock-names = "sdi", "apb_pclk";
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
+ };
+
+ sdi1_per2@80118000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ reg = <0x80118000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+
+ dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
+ <&dma 32 0 0x0>; /* Logical - MemToDev */
+ dma-names = "rx", "tx";
+
+ clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
+ clock-names = "sdi", "apb_pclk";
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
+ };
+
+ sdi2_per3@80005000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ reg = <0x80005000 0x1000>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+
+ dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
+ <&dma 28 0 0x0>; /* Logical - MemToDev */
+ dma-names = "rx", "tx";
+
+ clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
+ clock-names = "sdi", "apb_pclk";
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
+ };
+
+ sdi3_per2@80119000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ reg = <0x80119000 0x1000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+
+ dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
+ <&dma 41 0 0x0>; /* Logical - MemToDev */
+ dma-names = "rx", "tx";
+
+ clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
+ clock-names = "sdi", "apb_pclk";
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
+ };
+
+ sdi4_per2@80114000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ reg = <0x80114000 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+
+ dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
+ <&dma 42 0 0x0>; /* Logical - MemToDev */
+ dma-names = "rx", "tx";
+
+ clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
+ clock-names = "sdi", "apb_pclk";
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
+ };
+
+ sdi5_per3@80008000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ reg = <0x80008000 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+
+ dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
+ <&dma 43 0 0x0>; /* Logical - MemToDev */
+ dma-names = "rx", "tx";
+
+ clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
+ clock-names = "sdi", "apb_pclk";
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
+ };
+
+ sound {
+ compatible = "stericsson,snd-soc-mop500";
+ stericsson,cpu-dai = <&msp1 &msp3>;
+ };
+
+ msp0: msp@80123000 {
+ compatible = "stericsson,ux500-msp-i2s";
+ reg = <0x80123000 0x1000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ v-ape-supply = <&db8500_vape_reg>;
+
+ dmas = <&dma 31 0 0x12>, /* Logical - DevToMem -
HighPrio */
+ <&dma 31 0 0x10>; /* Logical - MemToDev -
HighPrio */
+ dma-names = "rx", "tx";
+
+ clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
+ clock-names = "msp", "apb_pclk";
+
+ status = "disabled";
+ };
+
+ msp1: msp@80124000 {
+ compatible = "stericsson,ux500-msp-i2s";
+ reg = <0x80124000 0x1000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ v-ape-supply = <&db8500_vape_reg>;
+
+ /* This DMA channel only exist on DB8500 v1 */
+ dmas = <&dma 30 0 0x10>; /* Logical - MemToDev -
HighPrio */
+ dma-names = "tx";
+
+ clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
+ clock-names = "msp", "apb_pclk";
+
+ status = "disabled";
+ };
+
+ // HDMI sound
+ msp2: msp@80117000 {
+ compatible = "stericsson,ux500-msp-i2s";
+ reg = <0x80117000 0x1000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ v-ape-supply = <&db8500_vape_reg>;
+
+ dmas = <&dma 14 0 0x12>, /* Logical - DevToMem -
HighPrio */
+ <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
+ HighPrio - Fixed */
+ dma-names = "rx", "tx";
+
+ clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
+ clock-names = "msp", "apb_pclk";
+
+ status = "disabled";
+ };
+
+ msp3: msp@80125000 {
+ compatible = "stericsson,ux500-msp-i2s";
+ reg = <0x80125000 0x1000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ v-ape-supply = <&db8500_vape_reg>;
+
+ /* This DMA channel only exist on DB8500 v2 */
+ dmas = <&dma 30 0 0x12>; /* Logical - DevToMem -
HighPrio */
+ dma-names = "rx";
+
+ clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
+ clock-names = "msp", "apb_pclk";
+
+ status = "disabled";
+ };
+
+ external-bus@50000000 {
+ compatible = "simple-bus";
+ reg = <0x50000000 0x4000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x50000000 0x4000000>;
+ status = "disabled";
+ };
+
+ gpu@a0300000 {
+ /*
+ * This block is referred to as "Smart Graphics Adapter
SGA500"
+ * in documentation but is in practice a pretty
straight-forward
+ * MALI-400 GPU block.
+ */
+ compatible = "stericsson,db8500-mali", "arm,mali-400";
+ reg = <0xa0300000 0x10000>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "combined";
+ clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk
PRCMU_SGACLK>;
+ clock-names = "bus", "core";
+ mali-supply = <&db8500_sga_reg>;
+ power-domains = <&pm_domains DOMAIN_VAPE>;
+ };
+
+ mcde@a0350000 {
+ compatible = "ste,mcde";
+ reg = <0xa0350000 0x1000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ epod-supply = <&db8500_b2r2_mcde_reg>;
+ clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock
*/
+ <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
+ <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */
+ clock-names = "mcde", "lcd", "hdmi";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ dsi0: dsi@a0351000 {
+ compatible = "ste,mcde-dsi";
+ reg = <0xa0351000 0x1000>;
+ clocks = <&prcmu_clk PRCMU_DSI0CLK>,
<&prcmu_clk PRCMU_DSI0ESCCLK>;
+ clock-names = "hs", "lp";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ dsi1: dsi@a0352000 {
+ compatible = "ste,mcde-dsi";
+ reg = <0xa0352000 0x1000>;
+ clocks = <&prcmu_clk PRCMU_DSI1CLK>,
<&prcmu_clk PRCMU_DSI1ESCCLK>;
+ clock-names = "hs", "lp";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ dsi2: dsi@a0353000 {
+ compatible = "ste,mcde-dsi";
+ reg = <0xa0353000 0x1000>;
+ /* This DSI port only has the Low Power /
Energy Save clock */
+ clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
+ clock-names = "lp";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cryp@a03cb000 {
+ compatible = "stericsson,ux500-cryp";
+ reg = <0xa03cb000 0x1000>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+
+ v-ape-supply = <&db8500_vape_reg>;
+ clocks = <&prcc_pclk 6 1>;
+ };
+
+ hash@a03c2000 {
+ compatible = "stericsson,ux500-hash";
+ reg = <0xa03c2000 0x1000>;
+
+ v-ape-supply = <&db8500_vape_reg>;
+ clocks = <&prcc_pclk 6 2>;
+ };
+ };
+};
diff --git a/include/dt-bindings/arm/ux500_pm_domains.h
b/include/dt-bindings/arm/ux500_pm_domains.h
new file mode 100644
index 0000000000..9bd764f0c9
--- /dev/null
+++ b/include/dt-bindings/arm/ux500_pm_domains.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2014 Linaro Ltd.
+ *
+ * Author: Ulf Hansson <ulf.hans...@linaro.org>
+ */
+#ifndef _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H
+#define _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H
+
+#define DOMAIN_VAPE 0
+
+/* Number of PM domains. */
+#define NR_DOMAINS (DOMAIN_VAPE + 1)
+
+#endif
diff --git a/include/dt-bindings/clock/ste-ab8500.h
b/include/dt-bindings/clock/ste-ab8500.h
new file mode 100644
index 0000000000..fb42dd0cab
--- /dev/null
+++ b/include/dt-bindings/clock/ste-ab8500.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __STE_CLK_AB8500_H__
+#define __STE_CLK_AB8500_H__
+
+#define AB8500_SYSCLK_BUF2 0
+#define AB8500_SYSCLK_BUF3 1
+#define AB8500_SYSCLK_BUF4 2
+#define AB8500_SYSCLK_ULP 3
+#define AB8500_SYSCLK_INT 4
+#define AB8500_SYSCLK_AUDIO 5
+
+#endif
diff --git a/include/dt-bindings/mfd/dbx500-prcmu.h
b/include/dt-bindings/mfd/dbx500-prcmu.h
new file mode 100644
index 0000000000..0404bcc47d
--- /dev/null
+++ b/include/dt-bindings/mfd/dbx500-prcmu.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for the PRCMU bindings.
+ *
+ */
+
+#ifndef _DT_BINDINGS_MFD_PRCMU_H
+#define _DT_BINDINGS_MFD_PRCMU_H
+
+/*
+ * Clock identifiers.
+ */
+#define ARMCLK 0
+#define PRCMU_ACLK 1
+#define PRCMU_SVAMMCSPCLK 2
+#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */
+#define PRCMU_SIACLK 3
+#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */
+#define PRCMU_SGACLK 4
+#define PRCMU_UARTCLK 5
+#define PRCMU_MSP02CLK 6
+#define PRCMU_MSP1CLK 7
+#define PRCMU_I2CCLK 8
+#define PRCMU_SDMMCCLK 9
+#define PRCMU_SLIMCLK 10
+#define PRCMU_CAMCLK 10 /* DBx540 only. */
+#define PRCMU_PER1CLK 11
+#define PRCMU_PER2CLK 12
+#define PRCMU_PER3CLK 13
+#define PRCMU_PER5CLK 14
+#define PRCMU_PER6CLK 15
+#define PRCMU_PER7CLK 16
+#define PRCMU_LCDCLK 17
+#define PRCMU_BMLCLK 18
+#define PRCMU_HSITXCLK 19
+#define PRCMU_HSIRXCLK 20
+#define PRCMU_HDMICLK 21
+#define PRCMU_APEATCLK 22
+#define PRCMU_APETRACECLK 23
+#define PRCMU_MCDECLK 24
+#define PRCMU_IPI2CCLK 25
+#define PRCMU_DSIALTCLK 26
+#define PRCMU_DMACLK 27
+#define PRCMU_B2R2CLK 28
+#define PRCMU_TVCLK 29
+#define SPARE_UNIPROCLK 30
+#define PRCMU_SSPCLK 31
+#define PRCMU_RNGCLK 32
+#define PRCMU_UICCCLK 33
+#define PRCMU_G1CLK 34 /* DBx540 only. */
+#define PRCMU_HVACLK 35 /* DBx540 only. */
+#define PRCMU_SPARE1CLK 36
+#define PRCMU_SPARE2CLK 37
+
+#define PRCMU_NUM_REG_CLOCKS 38
+
+#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS
+#define PRCMU_SYSCLK 39
+#define PRCMU_CDCLK 40
+#define PRCMU_TIMCLK 41
+#define PRCMU_PLLSOC0 42
+#define PRCMU_PLLSOC1 43
+#define PRCMU_ARMSS 44
+#define PRCMU_PLLDDR 45
+
+/* DSI Clocks */
+#define PRCMU_PLLDSI 46
+#define PRCMU_DSI0CLK 47
+#define PRCMU_DSI1CLK 48
+#define PRCMU_DSI0ESCCLK 49
+#define PRCMU_DSI1ESCCLK 50
+#define PRCMU_DSI2ESCCLK 51
+
+/* LCD DSI PLL - Ux540 only */
+#define PRCMU_PLLDSI_LCD 52
+#define PRCMU_DSI0CLK_LCD 53
+#define PRCMU_DSI1CLK_LCD 54
+#define PRCMU_DSI0ESCCLK_LCD 55
+#define PRCMU_DSI1ESCCLK_LCD 56
+#define PRCMU_DSI2ESCCLK_LCD 57
+
+#define PRCMU_NUM_CLKS 58
+
+#endif
--
2.24.1
