On 11/21/19 1:11 AM, AKASHI Takahiro wrote:
# This patch set is a prerequisite for UEFI secure boot.
The current rsa_verify() requires five parameters for a RSA public key
for efficiency while RSA, in theory, requires only two. In addition,
those parameters are expected to come from FIT image.
So this function won't fit very well when we want to use it for the purpose
of implementing UEFI secure boot, in particular, image authentication
as well as variable authentication, where the essential two parameters
are set to be retrieved from one of X509 certificates in signature
database.
So, in this patch, additional three parameters will be calculated
on the fly when rsa_verify() is called without fdt which should contain
parameters above.
This calculation heavily relies on "big-number (or multi-precision)
library." Therefore some routines from BearSSL[1] under MIT license are
imported in this implementation. See Patch#4.
# Please let me know if this is not appropriate.
Prerequisite:
* public key parser in my "import x509/pkcs7 parser" patch[2]
# Checkpatch will complain with lots of warnings/errors, but
# I intentionally don't fix them for maximum maintainability.
[1] https://bearssl.org/
[2] https://lists.denx.de/pipermail/u-boot/2019-November/390127.html
Changes in v4 (Nov 21, 2019)
* rebased to v2020.01-rc3
* change a function prototype of rsa_gen_key_prop() to return an error
code (patch#4,#5)
* re-order include files in alphabetical order (patch#6)
* add some comments per Simon's review comments
Changes in v3 (Nov 13, 2019)
* remove RSA_VERIFY_WITH_PKEY, which is to be added in patch#2 (patch#1)
* modify unit test Kconfg due to removal of test/lib/Kconfig (patch#6)
Changes in v2 (Oct 29, 2019)
* fix build errors at Travis CI
* not include linux/kconfig.h (patch#1)
* add a separate patch for adding CONFIG_RSA_VERIFY_WITH_PKEY (patch#2)
* take a prerequisite patch from my "secure boot patch" (patch#3)
* add a dependency on RSA_PUBLIC_KEY_PARSER (patch#4)
* remove "inline" directives (patch#4)
* add function descriptions, which mostly come from BearSSL's src/inner.h
(patch#4)
* improve Kconfig help text after Simon's comment (patch#5)
* add function description of rsa_verify_with_pkey() (patch#5)
* modify rsa_verify() to use "if (CONFIG_IS_ENABLED(...) " style
rather than "#ifdef CONFIG_..." (patch#5)
* add function tests (patch#6)
Changes in v1 (Oct 9, 2019)
* fix a build error on pine64-lts_defconfig (reported by Heinrich)
by defining FIT_IMAGE_ENABLE_VERIFY flag and adding
SPL_RSA_VERIFY config (patch#1)
* remove FIT-specific code from image-sig.c and put them to new
image-fit-sig.c to allow us to disable CONFIG_FIT_SIGNATURE (patch#1)
* compile rsa-keyprop.c only if necessary (i.e. if
CONFIG_RSA_VERIFY_WITH_PKEY) (patch#2)
* add SPDX license identifier in rsa-keyprop.c (patch#2)
* include <common.h> instead of <stdio.h> (patch#2)
* use U-Boot's byteorder helper functions instead of BearSSL's (patch#2)
I tried to test Takahiro's patches and have the following problem:
When I add CONFIG_RSA=y, CONFIG_RSA_SOFTWARE_EXP=y to
pine64-lts_defconfig SPL restarts again and again after
"BL31: Preparing for EL3 exit to normal world ... SPSR = 0x3c9".
CONFIG_SPL_RSA does not make a difference. See below
So even without Takahiro's patches RSA is a complete failure on this board.
Best regards
Heinrich
U-Boot SPL 2020.01-00620-g2d2f91a480 (Jan 18 2020 - 20:10:54 +0000)
DRAM: 2048 MiB
Trying to boot from MMC1
NOTICE: BL31: v2.2(debug):v2.2-351-g5d3ee0764
NOTICE: BL31: Built : 06:50:11, Jan 17 2020
NOTICE: BL31: Detected Allwinner A64/H64/R18 SoC (1689)
NOTICE: BL31: Found U-Boot DTB at 0x408ef20, model: Pine64 LTS
INFO: ARM GICv2 driver initialized
INFO: Configuring SPC Controller
INFO: PMIC: Probing AXP803 on RSB
INFO: PMIC: dcdc1 voltage: 3.300V
INFO: PMIC: dcdc5 voltage: 1.200V
INFO: PMIC: dcdc6 voltage: 1.100V
INFO: PMIC: dldo1 voltage: 3.300V
INFO: PMIC: Enabling DC SW
INFO: BL31: Platform setup done
INFO: BL31: Initializing runtime services
INFO: BL31: cortex_a53: CPU workaround for 843419 was applied
INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x4a000000
INFO: SPSR = 0x3c9
U-Boot SPL 2020.01-00620-g2d2f91a480 (Jan 18 2020 - 20:10:54 +0000)
DRAM: 2048 MiB
Trying to boot from MMC1
NOTICE: BL31: v2.2(debug):v2.2-351-g5d3ee0764
NOTICE: BL31: Built : 06:50:11, Jan 17 2020
NOTICE: BL31: Detected Allwinner A64/H64/R18 SoC (1689)
NOTICE: BL31: Found U-Boot DTB at 0x408ef20, model: Pine64 LTS
INFO: ARM GICv2 driver initialized
INFO: Configuring SPC Controller
INFO: PMIC: Probing AXP803 on RSB
INFO: PMIC: dcdc1 voltage: 3.300V
INFO: PMIC: dcdc5 voltage: 1.200V
INFO: PMIC: dcdc6 voltage: 1.100V
INFO: PMIC: dldo1 voltage: 3.300V
INFO: PMIC: Enabling DC SW
INFO: BL31: Platform setup done
INFO: BL31: Initializing runtime services
INFO: BL31: cortex_a53: CPU workaround for 843419 was applied
INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x4a000000
INFO: SPSR = 0x3c9
...
