Hi Weijie,
I attach my, apparently working, port to VoCore2 SoM.
These patchsets are on top of Your 21 patch rewrite of MT7628 board,
While the first patchset is relatively straightforward, but does not include
MMC handling, to enable it I had to backport from Linux Kernel several
pieces, essentially clock and interrupt handling.
Those drivers appear written by You.
I am unsure if this is really needed or if there is some other (perhaps
cleaner)
way to enable MMC.
As said this seems to work for me, but I would like to contribute this
board upstream, in the best possible way.
Please let me know how I should proceed.
Best Regards and Thanks in Advance
>From bee4d1255357c2e1f7546cdde3641380e95348e8 Mon Sep 17 00:00:00 2001
From: Mauro Condarelli <mc5...@mclink.it>
Date: Mon, 20 Jan 2020 21:40:13 +0100
Subject: [PATCH 1/2] mtmips: Add support for VoCore2 board
Signed-off-by: Mauro Condarelli <mc5...@mclink.it>
---
arch/mips/dts/Makefile | 1 +
arch/mips/dts/vocore_vocore2.dts | 64 +++++++++++++++++++++++++++++
arch/mips/mach-mtmips/Kconfig | 9 ++++
board/vocore/vocore2/Kconfig | 11 +++++
board/vocore/vocore2/Makefile | 2 +
board/vocore/vocore2/board.c | 35 ++++++++++++++++
configs/vocore2_defconfig | 69 +++++++++++++++++++++++++++++++
include/configs/vocore2.h | 70 ++++++++++++++++++++++++++++++++
8 files changed, 261 insertions(+)
create mode 100644 arch/mips/dts/vocore_vocore2.dts
create mode 100644 board/vocore/vocore2/Kconfig
create mode 100644 board/vocore/vocore2/Makefile
create mode 100644 board/vocore/vocore2/board.c
create mode 100644 configs/vocore2_defconfig
create mode 100644 include/configs/vocore2.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index cbd0c8bc8b..f711e9fb59 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -23,6 +23,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f...@st1704.dtb
dtb-$(CONFIG_BOARD_SFR_NB4_SER) += sfr,nb4-ser.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
+dtb-$(CONFIG_BOARD_VOCORE2) += vocore_vocore2.dtb
dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
diff --git a/arch/mips/dts/vocore_vocore2.dts b/arch/mips/dts/vocore_vocore2.dts
new file mode 100644
index 0000000000..ec9df70f55
--- /dev/null
+++ b/arch/mips/dts/vocore_vocore2.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Mauro Condarelli <mc5...@mclink.it>
+ */
+
+/dts-v1/;
+
+#include "mt7628a.dtsi"
+
+/ {
+ compatible = "vocore,vocore2", "ralink,mt7628a-soc";
+ model = "VoCore2";
+
+ aliases {
+ serial0 = &uart2;
+ spi0 = &spi0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS2,115200";
+ stdout-path = &uart2;
+ };
+};
+
+&pinctrl {
+ state_default: pin_state {
+ p0led {
+ groups = "p0led_a";
+ function = "led";
+ };
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <2>;
+
+ nor0: spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <25000000>;
+ reg = <0>;
+ };
+};
+
+ð {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ephy_iot_mode>;
+ mediatek,poll-link-phy = <0>;
+};
+
+&mmc {
+ status = "okay";
+};
diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig
index 1cd1d16022..3546b8f4f1 100644
--- a/arch/mips/mach-mtmips/Kconfig
+++ b/arch/mips/mach-mtmips/Kconfig
@@ -84,6 +84,14 @@ config BOARD_MT7628_RFB
SPI-NOR flash, 1 built-in switch with 5 ports, 1 UART, 1 USB host,
1 SDXC, 1 PCIe socket and JTAG pins.
+config BOARD_VOCORE2
+ bool "VoCore2"
+ depends on SOC_MT7628
+ select SUPPORTS_BOOT_RAM
+ help
+ VoCore VoCore2 board has a MT7628 SoC with 128 MiB of RAM
+ and 16 MiB of flash (SPI).
+
endchoice
config SPL_UART2_SPIS_PINMUX
@@ -97,5 +105,6 @@ config SPL_UART2_SPIS_PINMUX
source "board/gardena/smart-gateway-mt7688/Kconfig"
source "board/mediatek/mt7628/Kconfig"
source "board/seeed/linkit-smart-7688/Kconfig"
+source "board/vocore/vocore2/Kconfig"
endmenu
diff --git a/board/vocore/vocore2/Kconfig b/board/vocore/vocore2/Kconfig
new file mode 100644
index 0000000000..9178c3ab32
--- /dev/null
+++ b/board/vocore/vocore2/Kconfig
@@ -0,0 +1,11 @@
+if BOARD_VOCORE2
+config SYS_BOARD
+ default "vocore2"
+
+config SYS_VENDOR
+ default "vocore"
+
+config SYS_CONFIG_NAME
+ default "vocore2"
+
+endif
diff --git a/board/vocore/vocore2/Makefile b/board/vocore/vocore2/Makefile
new file mode 100644
index 0000000000..4b162318c2
--- /dev/null
+++ b/board/vocore/vocore2/Makefile
@@ -0,0 +1,2 @@
+
+obj-y := board.o
diff --git a/board/vocore/vocore2/board.c b/board/vocore/vocore2/board.c
new file mode 100644
index 0000000000..1ab430247b
--- /dev/null
+++ b/board/vocore/vocore2/board.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Mauro Condarelli <mc5...@mclink.it>
+ *
+ * Note: this is largely copied from:
+ * board/seeed/linkit_smart_7688/board.c
+ * Copyright (C) 2018 Stefan Roese <s...@denx.de>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MT76XX_GPIO1_MODE 0x10000060
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_debug_uart_init(void)
+{
+ void __iomem *gpio_mode;
+
+ /* Select UART2 mode instead of GPIO mode (default) */
+ gpio_mode = ioremap_nocache(MT76XX_GPIO1_MODE, 0x100);
+ clrbits_le32(gpio_mode, GENMASK(27, 26));
+}
+
+int board_early_init_f(void)
+{
+ /*
+ * The pin muxing of UART2 also needs to be done, if debug uart
+ * is not enabled. So we need to call this function here as well.
+ */
+ board_debug_uart_init();
+
+ return 0;
+}
diff --git a/configs/vocore2_defconfig b/configs/vocore2_defconfig
new file mode 100644
index 0000000000..6cc85ae64a
--- /dev/null
+++ b/configs/vocore2_defconfig
@@ -0,0 +1,69 @@
+CONFIG_MIPS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x5E000
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x20000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_ARCH_MTMIPS=y
+CONFIG_BOARD_VOCORE2=y
+CONFIG_SPL_UART2_SPIS_PINMUX=y
+CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
+CONFIG_MTDPARTS_DEFAULT="spi0.0:376k(u-boot),4k(env),4k(factory),2688k(kernel),-(filesystem)"
+CONFIG_DEFAULT_DEVICE_TREE="vocore_vocore2"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
+CONFIG_SPL_DM=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_BLK=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_MTD=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+# CONFIG_DM_ETH is not set
+CONFIG_PHY=y
+CONFIG_MT76X8_USB_PHY=y
+CONFIG_SPI=y
+CONFIG_MT7621_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_FS_EXT4=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h
new file mode 100644
index 0000000000..e90c3c2d74
--- /dev/null
+++ b/include/configs/vocore2.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Mauro Condarelli <mc5...@mclink.it>
+ */
+
+#ifndef __VOCORE2_CONFIG_H__
+#define __VOCORE2_CONFIG_H__
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+
+/* SPL */
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_SYS_UBOOT_BASE (CONFIG_SPL_TEXT_BASE + 0x4000)
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPL_BSS_START_ADDR 0x80010000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x10000
+#define CONFIG_SPL_MAX_SIZE 0x10000
+
+/* Serial SPL */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_CLK 40000000
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_COM3 0xb0000e00
+#define CONFIG_CONS_INDEX 3
+
+#endif
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+ 230400, 460800, 921600 }
+
+/* RAM */
+#define CONFIG_SYS_MEMTEST_START 0x80100000
+#define CONFIG_SYS_MEMTEST_END 0x80400000
+
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
+#define CONFIG_SYS_CBSIZE 512
+
+/* U-Boot */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+/* Environment settings */
+#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
+#endif
+
+/*
+ * Environment is right behind U-Boot in flash. Make sure U-Boot
+ * doesn't grow into the environment area.
+ */
+//#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
+
+#endif//__VOCORE2_CONFIG_H__
--
2.25.0
>From 602ac7d1424ce500e7c818431d7aa8aa97b654f2 Mon Sep 17 00:00:00 2001
From: Mauro Condarelli <mc5...@mclink.it>
Date: Tue, 21 Jan 2020 00:37:43 +0100
Subject: [PATCH 2/2] mips: mtmips: vocore2: add support for MMC/SD
Signed-off-by: Mauro Condarelli <mc5...@mclink.it>
---
arch/mips/dts/mt7628a.dtsi | 48 ++++++++++++++++++++-
configs/vocore2_defconfig | 10 ++++-
drivers/clk/Kconfig | 8 ++++
drivers/clk/Makefile | 1 +
drivers/clk/clk-mtmips-cg.c | 63 ++++++++++++++++++++++++++++
drivers/phy/Kconfig | 2 +
include/configs/vocore2.h | 22 +++++-----
include/dt-bindings/clk/mt7628-clk.h | 31 ++++++++++++++
8 files changed, 172 insertions(+), 13 deletions(-)
create mode 100644 drivers/clk/clk-mtmips-cg.c
create mode 100644 include/dt-bindings/clk/mt7628-clk.h
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi
index f265cb6ad9..a47309732a 100644
--- a/arch/mips/dts/mt7628a.dtsi
+++ b/arch/mips/dts/mt7628a.dtsi
@@ -7,6 +7,18 @@
#size-cells = <1>;
compatible = "ralink,mt7628a-soc";
+ resetc: reset-controller {
+ compatible = "ralink,rt2880-reset";
+ #reset-cells = <1>;
+ };
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
clk48m: clk48m@0 {
compatible = "fixed-clock";
@@ -41,6 +53,12 @@
u-boot,dm-pre-reloc;
};
+ clkgate: clkgate@0x30 {
+ reg = <0x30 0x4>;
+ compatible = "mediatek,mtmips-clk-gate";
+ #clock-cells = <1>;
+ };
+
rstctrl: rstctrl@0x34 {
reg = <0x34 0x4>;
compatible = "mediatek,mtmips-reset";
@@ -213,6 +231,24 @@
reset-names = "wdt";
};
+ intc: interrupt-controller@200 {
+ compatible = "ralink,rt2880-intc";
+ reg = <0x200 0x100>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ resets = <&resetc 9>;
+ reset-names = "intc";
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+
+ ralink,intc-registers = <0x9c 0xa0
+ 0x6c 0xa4
+ 0x80 0x78>;
+ };
+
gpio@600 {
#address-cells = <1>;
#size-cells = <0>;
@@ -346,9 +382,19 @@
builtin-cd = <1>;
r_smpl = <1>;
- clocks = <&clk48m>, <&clkctrl CLK_SDXC>;
+ interrupt-parent = <&intc>;
+ interrupts = <14>;
+
+ clocks = <&clk48m>, <&clk48m>;
clock-names = "source", "hclk";
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&sd_iot_mode>;
+ pinctrl-1 = <&sd_iot_mode>;
+
+ vmmc-supply = <&clk48m>;
+ vqmmc-supply = <&clk48m>;
+
resets = <&rstctrl MT7628_SDXC_RST>;
status = "disabled";
diff --git a/configs/vocore2_defconfig b/configs/vocore2_defconfig
index 6cc85ae64a..9758038dd7 100644
--- a/configs/vocore2_defconfig
+++ b/configs/vocore2_defconfig
@@ -28,10 +28,12 @@ CONFIG_CMD_LICENSE=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_MTDPARTS=y
@@ -43,10 +45,13 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_SPL_DM=y
# CONFIG_DM_DEVICE_REMOVE is not set
-CONFIG_BLK=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
+CONFIG_MMC=y
+CONFIG_DM_MMC=y
+# CONFIG_MMC_HW_PARTITIONING is not set
+CONFIG_MMC_MTK=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
@@ -57,6 +62,7 @@ CONFIG_SPI_FLASH_MTD=y
# CONFIG_DM_ETH is not set
CONFIG_PHY=y
CONFIG_MT76X8_USB_PHY=y
+# CONFIG_RAM_ROCKCHIP_DEBUG is not set
CONFIG_SPI=y
CONFIG_MT7621_SPI=y
CONFIG_USB=y
@@ -64,6 +70,8 @@ CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
+CONFIG_WDT=y
+CONFIG_WDT_MT7621=y
CONFIG_FS_EXT4=y
CONFIG_LZMA=y
CONFIG_LZO=y
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 16d4237f89..fbe6ae86d6 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -176,4 +176,12 @@ config SANDBOX_CLK_CCF
Enable this option if you want to test the Linux kernel's Common
Clock Framework [CCF] code in U-Boot's Sandbox clock driver.
+config CLK_MTMIPS_GATE
+ bool "Enable clock gating driver for MediaTek MIPS platform"
+ depends on CLK && ARCH_MTMIPS
+ default y
+ help
+ Enable clock gating driver for MediaTek MIPS platform.
+ This driver supports only clock enable and disable.
+
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 06131edb9f..585335be25 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
+obj-$(CONFIG_CLK_MTMIPS_GATE) += clk-mtmips-cg.o
obj-$(CONFIG_CLK_OWL) += owl/
obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_CLK_SIFIVE) += sifive/
diff --git a/drivers/clk/clk-mtmips-cg.c b/drivers/clk/clk-mtmips-cg.c
new file mode 100644
index 0000000000..0221d95aed
--- /dev/null
+++ b/drivers/clk/clk-mtmips-cg.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie....@mediatek.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/io.h>
+
+struct mtmips_clk_gate_priv {
+ void __iomem *base;
+};
+
+static int mtmips_clk_gate_enable(struct clk *clk)
+{
+ struct mtmips_clk_gate_priv *priv = dev_get_priv(clk->dev);
+
+ setbits_32(priv->base, BIT(clk->id));
+
+ return 0;
+}
+
+static int mtmips_clk_gate_disable(struct clk *clk)
+{
+ struct mtmips_clk_gate_priv *priv = dev_get_priv(clk->dev);
+
+ clrbits_32(priv->base, BIT(clk->id));
+
+ return 0;
+}
+
+const struct clk_ops mtmips_clk_gate_ops = {
+ .enable = mtmips_clk_gate_enable,
+ .disable = mtmips_clk_gate_disable,
+};
+
+static int mtmips_clk_gate_probe(struct udevice *dev)
+{
+ struct mtmips_clk_gate_priv *priv = dev_get_priv(dev);
+
+ priv->base = (void __iomem *)dev_remap_addr_index(dev, 0);
+ if (!priv->base)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct udevice_id mtmips_clk_gate_ids[] = {
+ { .compatible = "mediatek,mtmips-clk-gate" },
+ { }
+};
+
+U_BOOT_DRIVER(mtmips_clk_gate) = {
+ .name = "mtmips-clk-gate",
+ .id = UCLASS_CLK,
+ .of_match = mtmips_clk_gate_ids,
+ .probe = mtmips_clk_gate_probe,
+ .priv_auto_alloc_size = sizeof(struct mtmips_clk_gate_priv),
+ .ops = &mtmips_clk_gate_ops,
+};
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index a72f34f0d4..d9acda2c6a 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -201,6 +201,8 @@ config MT76X8_USB_PHY
bool "MediaTek MT76x8 (7628/88) USB PHY support"
depends on PHY
depends on SOC_MT7628
+ select CLK
+ select DM_RESET
help
Support the USB PHY in MT76x8 SoCs
diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h
index e90c3c2d74..8006cf8804 100644
--- a/include/configs/vocore2.h
+++ b/include/configs/vocore2.h
@@ -7,14 +7,14 @@
#define __VOCORE2_CONFIG_H__
/* CPU */
-#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
+#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x200000)
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
@@ -42,17 +42,17 @@
230400, 460800, 921600 }
/* RAM */
-#define CONFIG_SYS_MEMTEST_START 0x80100000
-#define CONFIG_SYS_MEMTEST_END 0x80400000
+#define CONFIG_SYS_MEMTEST_START 0x80100000
+#define CONFIG_SYS_MEMTEST_END 0x80400000
/* Memory usage */
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
-#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
-#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
+#define CONFIG_SYS_CBSIZE 512
/* U-Boot */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
/* Environment settings */
#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
diff --git a/include/dt-bindings/clk/mt7628-clk.h b/include/dt-bindings/clk/mt7628-clk.h
new file mode 100644
index 0000000000..6784d6e50b
--- /dev/null
+++ b/include/dt-bindings/clk/mt7628-clk.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ *
+ * Author: Weijie Gao <weijie....@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_MT7628_CLK_H_
+#define _DT_BINDINGS_MT7628_CLK_H_
+
+#define MT7628_PWM_CLK 31
+#define MT7628_SDXC_CLK 30
+#define MT7628_CRYPTO_CLK 29
+#define MT7628_MIPS_CNT_CLK 28
+#define MT7628_PCIE_CLK 26
+#define MT7628_UPHY_CLK 25
+#define MT7628_ETH_CLK 23
+#define MT7628_UART2_CLK 20
+#define MT7628_UART1_CLK 19
+#define MT7628_SPI_CLK 18
+#define MT7628_I2S_CLK 17
+#define MT7628_I2C_CLK 16
+#define MT7628_GDMA_CLK 14
+#define MT7628_PIO_CLK 13
+#define MT7628_UART0_CLK 12
+#define MT7628_PCM_CLK 11
+#define MT7628_MC_CLK 10
+#define MT7628_INT_CLK 9
+#define MT7628_TIMER_CLK 8
+
+#endif /* _DT_BINDINGS_MT7628_CLK_H_ */
--
2.25.0
