Add support for this new field in the common code used by most x86 CPU
drivers.
Signed-off-by: Simon Glass <s...@chromium.org>
---
arch/x86/cpu/i386/cpu.c | 23 +++++++++++++++++++++++
arch/x86/cpu/intel_common/cpu.c | 1 +
arch/x86/include/asm/cpu.h | 9 +++++++++
3 files changed, 33 insertions(+)
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index 2b27617ca3..5904cdcd48 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -31,6 +31,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#define CPUID_FEATURE_PAE BIT(6)
+#define CPUID_FEATURE_PSE36 BIT(17)
+#define CPUID_FEAURE_HTT BIT(28)
+
/*
* Constructor for a conventional segment GDT (or LDT) entry
* This is a macro so it can be used in initialisers
@@ -376,6 +380,25 @@ static void setup_identity(void)
}
}
+static uint cpu_cpuid_extended_level(void)
+{
+ return cpuid_eax(0x80000000);
+}
+
+int cpu_phys_address_size(void)
+{
+ if (!has_cpuid())
+ return 32;
+
+ if (cpu_cpuid_extended_level() >= 0x80000008)
+ return cpuid_eax(0x80000008) & 0xff;
+
+ if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
+ return 36;
+
+ return 32;
+}
+
/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
static void setup_pci_ram_top(void)
{
diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c
index 106ff41e23..f45d94825f 100644
--- a/arch/x86/cpu/intel_common/cpu.c
+++ b/arch/x86/cpu/intel_common/cpu.c
@@ -126,6 +126,7 @@ int cpu_intel_get_info(struct cpu_info *info, int bclk)
info->cpu_freq = ((msr.lo >> 8) & 0xff) * bclk * 1000000;
info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
+ info->address_width = cpu_phys_address_size();
return 0;
}
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 21a05dab7d..5b001bbee2 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -288,4 +288,13 @@ u32 cpu_get_family_model(void);
*/
u32 cpu_get_stepping(void);
+/**
+ * cpu_phys_address_size() - Get the physical address size in bits
+ *
+ * This is 32 for older CPUs but newer ones may support 36.
+ *
+ * @return address size (typically 32 or 36)
+ */
+int cpu_phys_address_size(void);
+
#endif
--
2.25.0.341.g760bfbb309-goog
