The add instruction on risc-v can have any three sources and targets, so there
is no need for an intermediate mov.
Signed-off-by: Sean Anderson <sean...@gmail.com>
---
arch/riscv/cpu/start.S | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 1a55b7d570..365163ad19 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -359,9 +359,8 @@ relocate_secondary_harts:
call_board_init_r:
jal invalidate_icache_all
jal flush_dcache_all
- la t0, board_init_r
- mv t4, t0 /* offset of board_init_r() */
- add t4, t4, t6 /* real address of board_init_r() */
+ la t0, board_init_r /* offset of board_init_r() */
+ add t4, t0, t6 /* real address of board_init_r() */
/*
* setup parameters for board_init_r
*/
--
2.25.0
