This has been tested on at91sam9263 and STN8815.
Again, I didn't check if it has bad effects
on non-arm926 cores.
Initially I had a "done" bit to only set up page tables
at the beginning. However, since the aligmnent requirement
was for the whole object file, this extra integer tool 16kB
in BSS, so I chose to remove it.
Also, note not all boards use PHYS_SDRAM, but it looks like
it's the most used name (more than CONFIG_SYS_DRAM_BASE for
example).
rebased for full arm relocation from Heiko Schocher <h...@denx.de>
Signed-off-by: Alessandro Rubini <rub...@gnudd.com>
Signed-off-by: Heiko Schocher <h...@denx.de>
---
- changes since v1:
- add possibilty to use dcache in write_through mode, as Nick
Thompson suggested.
- use the ram setup info in bd_t to setup the TLB
- added my Signed-off-by upon consultation with Alessandro
arch/arm/lib/cache-cp15.c | 51 +++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 51 insertions(+), 0 deletions(-)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 62ed54f..5cbfe42 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -25,6 +25,15 @@
#include <asm/system.h>
#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
+
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+#define CACHE_SETUP 0x1a
+#else
+#define CACHE_SETUP 0x1e
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
static void cp_delay (void)
{
volatile int i;
@@ -32,6 +41,40 @@ static void cp_delay (void)
/* copro seems to need some delay between reading and writing */
for (i = 0; i < 100; i++)
nop();
+ asm volatile("" : : : "memory");
+}
+
+/* to activate the MMU we need to set up virtual memory: use 1M areas in bss */
+static inline void mmu_setup(void)
+{
+ static u32 __attribute__((aligned(16384))) page_table[4096];
+ bd_t *bd = gd->bd;
+ int i, j;
+ u32 reg;
+
+ /* Set up an identity-mapping for all 4GB, rw for everyone */
+ for (i = 0; i < 4096; i++)
+ page_table[i] = i << 20 | (3 << 10) | 0x12;
+ /* Then, enable cacheable and bufferable for RAM only */
+ for (j = 0 < CONFIG_NR_DRAM_BANKS; j++) {
+ for (i = bd->bi_dram[j].start >> 20;
+ i < (bd->bi_dram[j].start + bd->bi_dram[j].size) >> 20;
+ i++) {
+ page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
+ }
+ }
+
+ /* Copy the page table address to cp15 */
+ asm volatile("mcr p15, 0, %0, c2, c0, 0"
+ : : "r" (page_table) : "memory");
+ /* Set the access control to all-supervisor */
+ asm volatile("mcr p15, 0, %0, c3, c0, 0"
+ : : "r" (~0));
+ /* and enable the mmu */
+ reg = get_cr(); /* get control reg. */
+ cp_delay();
+ set_cr(reg | CR_M);
+
}
/* cache_bit must be either CR_I or CR_C */
@@ -39,6 +82,9 @@ static void cache_enable(uint32_t cache_bit)
{
uint32_t reg;
+ /* The data cache is not active unless the mmu is enabled too */
+ if (cache_bit == CR_C)
+ mmu_setup();
reg = get_cr(); /* get control reg. */
cp_delay();
set_cr(reg | cache_bit);
@@ -49,6 +95,11 @@ static void cache_disable(uint32_t cache_bit)
{
uint32_t reg;
+ if (cache_bit == CR_C) {
+ /* if disabling data cache, disable mmu too */
+ cache_bit |= CR_M;
+ flush_cache(0, ~0);
+ }
reg = get_cr();
cp_delay();
set_cr(reg & ~cache_bit);
--
1.6.2.5
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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