(adding Tanmay who might be interested in the OpenOCD init sequence issue)

Le 02/08/2010 08:13, Albert ARIBAUD a écrit :
Hi,

Le 02/08/2010 05:35, Prafulla Wadaskar a écrit :

I tried tweaking MPP setup for SATA related stuff, it's multiplexed with UART 
and other I/Os (NAND),
What I observed: if I boot kernel with sata support, kernel sata driver works 
properly and I can detect and use IDE devices.

So I doubt MPP, I don't know kernel (latest stable) overrides MPP settings done 
by u-boot?? We can get some reference from there.

I went the low level route and compared MPP / GPIO settings (content of
0xf1010000, 0xf1010100, 0xf1010140) at original U-boot start and at
(patched) mainline u-boot start: three MPPs are set up differently,
namely MPP13 and 14 (original had UART 1 signals, mainline has SD
signals) and MPP29 (original had TS MP[9], mainline has GPIO).

I have taken the OpenRD schematics from GlobalScale Technologies, and I
have found no indication that these signals have anything to do with SATA.

Also, I have noticed that 'ide reset' may work on kirkwood dependending
on conditions yet imprecise, possibly related to whether an 'ide reset'
was already done from the original u-boot; also there are times when I
get garbled console output or no console at all.

These random issues could come from the fact I use OpenOCD to reset the
Open-RD client, set up the RAM and upload and run the u-boot image,
rather than rely on the kwbimage process -- that's because I don't want
to flash to NAND until I am sure the boot loader works enough -- and
there may be initialization differences between the kwbimage wrapper and
the OpenOCD init script. I'll have a look at that too, just in case.

I've had a look, and the OpenOCD config file for openrd has an incomplete init sequence, mostly concerning MPP settings. I've completed it and so far it seems to work better (I'll check/submit an update to the OpenOCD project for this).

As for the ATAPI issue as such, I'll try adding a delay between the
writes within the port initialization function, although I could find no
indication in the 88F6281 specs that such a delay is required or what
order of duration it should have.

I'll post my results at end of day today.

Actually two things were necessary to get ide reset to work reliably:

1) adding a delay between the writes to SControl. Experimentation showed this delay should be at least 41 us on my board. I have set it to 50 us to play safe on possible HW characteristics dispersions.

2) moving the call(s) to mvsata_ide_initialize_port() from board_init() function to function ide_preinit(), which is called just before an IDE reset if CONFIG_IDE_INIT is set -- accordingly, I added ide_preinit() to openrd_base.c and defined CONFIG_IDE_INIT in kirkwood.h.

Prafulla, can you try the patch attached above yours?

If this works, then I'll backport the above fixes to orion5x/edminiv2 and post a V7 patch.

Amicalement,
--
Albert.
diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h 
b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
index baf0c47..fb18ef7 100644
--- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h
+++ b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
@@ -68,6 +68,8 @@
 #define MVGBE0_BASE    KW_EGIGA0_BASE
 #define MVGBE1_BASE    KW_EGIGA1_BASE
 
+#define CONFIG_IDE_PREINIT
+
 #if defined (CONFIG_KW88F6281)
 #include <asm/arch/kw88f6281.h>
 #elif defined (CONFIG_KW88F6192)
diff --git a/board/Marvell/openrd_base/openrd_base.c 
b/board/Marvell/openrd_base/openrd_base.c
index 3c4c85d..5d0409f 100644
--- a/board/Marvell/openrd_base/openrd_base.c
+++ b/board/Marvell/openrd_base/openrd_base.c
@@ -111,16 +111,6 @@ int board_init(void)
        /* adress of boot parameters */
        gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
 
-#if defined(CONFIG_MVSATA_IDE)
-       /* Enable SATA port 0 if SATA IDE was configured */
-       mvsata_ide_initialize_port(
-               (struct mv_sata_port_registers *)
-               (KW_SATA_BASE + KW_SATA_PORT0_OFFSET));
-       mvsata_ide_initialize_port(
-               (struct mv_sata_port_registers *)
-               (KW_SATA_BASE + KW_SATA_PORT1_OFFSET));
-#endif
-
        return 0;
 }
 
@@ -169,3 +159,19 @@ void reset_phy(void)
        printf("88E1116 Initialized on %s\n", name);
 }
 #endif /* CONFIG_RESET_PHY_R */
+
+#if defined(CONFIG_MVSATA_IDE)
+int ide_preinit (void)
+{
+       /* Enable SATA port 0 if SATA IDE was configured */
+       mvsata_ide_initialize_port(
+               (struct mv_sata_port_registers *)
+               (KW_SATA_BASE + KW_SATA_PORT0_OFFSET));
+       mvsata_ide_initialize_port(
+               (struct mv_sata_port_registers *)
+               (KW_SATA_BASE + KW_SATA_PORT1_OFFSET));
+       /* return 0 as we always succeed */
+       return 0;
+}
+#endif
+
diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
index d44a42c..d27fa5c 100644
--- a/drivers/block/mvsata_ide.c
+++ b/drivers/block/mvsata_ide.c
@@ -54,6 +54,8 @@ void mvsata_ide_initialize_port(struct mvsata_port_registers 
*port)
 
        writel(reg, &port->scontrol);
 
+       udelay(41);
+
        reg = (reg & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE;
 
        writel(reg, &port->scontrol);
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