Hi Sean, On Mon, Feb 3, 2020 at 4:05 AM Sean Anderson <sean...@gmail.com> wrote: > > Some older processors (notably the Kendryte K210) use an older version of the > RISC-V privileged specification. The primary changes between the old and new > are > in virtual memory, and in the merging of three separate counter enable CSRs. > Using the new CSR on an old processor causes an illegal instruction exception. > This patch adds an option to use the old CSRs instead of the new one. > > Signed-off-by: Sean Anderson <sean...@gmail.com> > --- > Changes for v3: > - Renamed from "riscv: Add option to disable writes to mcounteren" > - Added original functionality back for older priv specs. > Changes for v2: > - Moved forward in the patch series > > arch/riscv/Kconfig | 10 ++++++++++ > arch/riscv/cpu/cpu.c | 6 ++++++ > arch/riscv/include/asm/csr.h | 6 ++++++ > 3 files changed, 22 insertions(+) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 85e15ebffa..87c40f6c4c 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -222,6 +222,16 @@ config XIP > from a NOR flash memory without copying the code to ram. > Say yes here if U-Boot boots from flash directly. > > +config RISCV_PRIV_1_9_1 > + bool "Use version 1.9.1 of the RISC-V priviledged specification"
typo: privileged > + help > + Older versions of the RISC-V priviledged specification had typo: privileged > + separate counter enable CSRs for each privilege mode. Writing > + to the unified mcounteren CSR on a processor implementing the > + old specification will result in an illegal instruction > + exception. In addition to counter CSR changes, the way virtual > + memory is configured was also changed. > + > config STACK_SIZE_SHIFT > int > default 14 > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c > index e457f6acbf..83cb6557cd 100644 > --- a/arch/riscv/cpu/cpu.c > +++ b/arch/riscv/cpu/cpu.c > @@ -89,7 +89,13 @@ int arch_cpu_init_dm(void) > * Enable perf counters for cycle, time, > * and instret counters only > */ > +#ifdef CONFIG_RISCV_PRIV_1_9_1 > + /* FIXME: Can't use the macro for some reason... */ This is weird ... > + csr_write(mscounteren, GENMASK(2, 0)); > + csr_write(mucounteren, GENMASK(2, 0)); > +#else > csr_write(CSR_MCOUNTEREN, GENMASK(2, 0)); > +#endif > > /* Disable paging */ > if (supports_extension('s')) > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index d1520743a2..c16b65d3f3 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -93,7 +93,13 @@ > #define CSR_MISA 0x301 > #define CSR_MIE 0x304 > #define CSR_MTVEC 0x305 > +#ifdef RISCV_PRIV_1_9_1 > +#define CSR_MUCOUNTEREN 0x320 > +#define CSR_MSCOUNTEREN 0x321 > +#define CSR_MHCOUNTEREN 0x322 > +#else > #define CSR_MCOUNTEREN 0x306 > +#endif > #define CSR_MSCRATCH 0x340 > #define CSR_MEPC 0x341 > #define CSR_MCAUSE 0x342 > -- Other than above, Reviewed-by: Bin Meng <bmeng...@gmail.com> Regards, Bin