Hi Sagar,
On Wed, Jan 29, 2020 at 2:02 AM Sagar Shrikant Kadam
<sagar.ka...@sifive.com> wrote:
>
> Add the number of chip select information to spi nodes which
> can be used by spi-uclass for error handling if invalid cs
> number passed from command.
>
> Signed-off-by: Sagar Shrikant Kadam <sagar.ka...@sifive.com>
> ---
> arch/riscv/dts/fu540-c000.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi
> index afa43c7..9c6ab21 100644
> --- a/arch/riscv/dts/fu540-c000.dtsi
> +++ b/arch/riscv/dts/fu540-c000.dtsi
> @@ -191,6 +191,7 @@
> clocks = <&prci PRCI_CLK_TLCLK>;
> #address-cells = <1>;
> #size-cells = <0>;
> + num-cs = <1>;
Why is this necessary? I can't find the codes that handle the num-cs
property. In the SiFive SPI driver, num_cs is determined from register
SIFIVE_SPI_REG_CSDEF.
> status = "disabled";
> };
> qspi1: spi@10041000 {
> @@ -202,6 +203,7 @@
> clocks = <&prci PRCI_CLK_TLCLK>;
> #address-cells = <1>;
> #size-cells = <0>;
> + num-cs = <1>;
> status = "disabled";
> };
> qspi2: spi@10050000 {
> @@ -212,6 +214,7 @@
> clocks = <&prci PRCI_CLK_TLCLK>;
> #address-cells = <1>;
> #size-cells = <0>;
> + num-cs = <1>;
> status = "disabled";
> };
> eth0: ethernet@10090000 {
> --
Regards,
Bin
