On 2/20/20 8:05 PM, Ang, Chee Hong wrote: >> On 2/20/20 3:27 AM, Ang, Chee Hong wrote: >>>> On 2/19/20 1:25 PM, chee.hong....@intel.com wrote: >>>> [...] >>>>> diff --git a/arch/arm/mach-socfpga/lowlevel_init.S >>>>> b/arch/arm/mach-socfpga/lowlevel_init.S >>>>> new file mode 100644 >>>>> index 0000000..68053a0 >>>>> --- /dev/null >>>>> +++ b/arch/arm/mach-socfpga/lowlevel_init.S >>>> >>>> This should be some lowlevel_init_64.S to make it clear it's only for >>>> arm64 platforms. >>> OK. It makes sense. Thanks. >>>> >>>>> @@ -0,0 +1,85 @@ >>>>> +/* SPDX-License-Identifier: GPL-2.0 */ >>>>> +/* >>>>> + * Copyright (C) 2019, Intel Corporation */ >>>>> + >>>>> +#include <asm-offsets.h> >>>>> +#include <config.h> >>>>> +#include <linux/linkage.h> >>>>> +#include <asm/macro.h> >>>>> + >>>>> +ENTRY(lowlevel_init) >>>>> + mov x29, lr /* Save LR */ >>>>> + >>>>> +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) #ifdef >>>>> +CONFIG_SPL_ATF >>>>> + branch_if_slave x0, 2f >>>>> +#else >>>>> + branch_if_slave x0, 1f >>>>> +#endif >>>>> + >>>>> + ldr x0, =GICD_BASE >>>>> + bl gic_init_secure >>>>> +#ifdef CONFIG_SPL_BUILD >>>>> + b 2f >>>>> +#else >>>>> + b 3f >>>>> +#endif >>>> >>>> Can't this be done in C code ? Can we reduce the ifdeffery ? >>> This lowlevel_init function is shared by SPL and U-Boot and they run >>> in slightly different flow. >> >> What does this 'different flow' mean ? > This has something to with multi-cores CPU such as A53. > For SPL, we need to make sure the slave CPUs (CPU1/2/3) trapped in a 'place' > Where they could be 'activated' by kernel for multi-processor environment. > It means the kernel get to 'activate' the slave CPUs from master CPU (CPU0) > U-Boot proper only run on master CPU (CPU0). The rest of slave CPUs > are trapped in the beginning of SPL waiting to be 'activated' > by kernel.
OK, so the secondary CPUs are spinning until the kernel releases them. > In U-Boot proper, only master CPU gets to run this code and it will just > do the basic GIC setup and skip the 'trap'. The 'trap' is to prevent the slave > CPUs from running the same SPL, ATF and U-Boot code as the master CPU in > parallel. Only single core (maser CPU) is needed for bootloaders and firmware. I would expect all the other SMP platforms solved this issue with secondary CPUs already, so why is agilex special ?