From: Chee Hong Ang <chee.hong....@intel.com>
Replace FDT API with more generic ofnode API.
Signed-off-by: Chee Hong Ang <chee.hong....@intel.com>
---
drivers/clk/altera/clk-arria10.c | 52 +++++++++++++++++++---------------------
1 file changed, 25 insertions(+), 27 deletions(-)
diff --git a/drivers/clk/altera/clk-arria10.c b/drivers/clk/altera/clk-arria10.c
index b7eed94..01bf5ec 100644
--- a/drivers/clk/altera/clk-arria10.c
+++ b/drivers/clk/altera/clk-arria10.c
@@ -190,16 +190,16 @@ static struct clk_ops socfpga_a10_clk_ops = {
static void socfpga_a10_handoff_workaround(struct udevice *dev)
{
struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
- const void *fdt = gd->fdt_blob;
struct clk_bulk *bulk = &plat->clks;
- int i, ret, offset = dev_of_offset(dev);
+ ofnode node = dev_ofnode(dev);
+ int i, ret;
static const char * const socfpga_a10_fixedclk_map[] = {
"osc1", "altera_arria10_hps_eosc1",
"cb_intosc_ls_clk", "altera_arria10_hps_cb_intosc_ls",
"f2s_free_clk", "altera_arria10_hps_f2h_free",
};
- if (fdt_node_check_compatible(fdt, offset, "fixed-clock"))
+ if (!ofnode_device_is_compatible(node, "fixed-clock"))
return;
for (i = 0; i < ARRAY_SIZE(socfpga_a10_fixedclk_map); i += 2)
@@ -227,42 +227,41 @@ static void socfpga_a10_handoff_workaround(struct udevice
*dev)
static int socfpga_a10_clk_bind(struct udevice *dev)
{
- const void *fdt = gd->fdt_blob;
- int offset = dev_of_offset(dev);
bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
const char *name;
+ ofnode node;
int ret;
- for (offset = fdt_first_subnode(fdt, offset);
- offset > 0;
- offset = fdt_next_subnode(fdt, offset)) {
- name = fdt_get_name(fdt, offset, NULL);
+ for (node = dev_read_first_subnode(dev);
+ ofnode_valid(node);
+ node = ofnode_next_subnode(node)) {
+ name = ofnode_get_name(node);
if (!name)
return -EINVAL;
if (!strcmp(name, "clocks")) {
- offset = fdt_first_subnode(fdt, offset);
- name = fdt_get_name(fdt, offset, NULL);
+ node = ofnode_first_subnode(node);
+ name = ofnode_get_name(node);
if (!name)
return -EINVAL;
}
/* Filter out supported sub-clock */
- if (fdt_node_check_compatible(fdt, offset,
+ if (!ofnode_device_is_compatible(node,
"altr,socfpga-a10-pll-clock") &&
- fdt_node_check_compatible(fdt, offset,
+ !ofnode_device_is_compatible(node,
"altr,socfpga-a10-perip-clk") &&
- fdt_node_check_compatible(fdt, offset,
+ !ofnode_device_is_compatible(node,
"altr,socfpga-a10-gate-clk") &&
- fdt_node_check_compatible(fdt, offset, "fixed-clock"))
+ !ofnode_device_is_compatible(node, "fixed-clock"))
continue;
if (pre_reloc_only &&
- !dm_ofnode_pre_reloc(offset_to_ofnode(offset)))
+ !dm_ofnode_pre_reloc(node))
continue;
ret = device_bind_driver_to_node(dev, "clk-a10", name,
- offset_to_ofnode(offset),
+ node,
NULL);
if (ret)
return ret;
@@ -273,18 +272,17 @@ static int socfpga_a10_clk_bind(struct udevice *dev)
static int socfpga_a10_clk_probe(struct udevice *dev)
{
+ ofnode node = dev_ofnode(dev);
struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
struct socfpga_a10_clk_platdata *pplat;
struct udevice *pdev;
- const void *fdt = gd->fdt_blob;
- int offset = dev_of_offset(dev);
clk_get_bulk(dev, &plat->clks);
socfpga_a10_handoff_workaround(dev);
- if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) {
- plat->regs = devfdt_get_addr(dev);
+ if (ofnode_device_is_compatible(node, "altr,clk-mgr")) {
+ plat->regs = ofnode_get_addr(node);
} else {
pdev = dev_get_parent(dev);
if (!pdev)
@@ -298,18 +296,18 @@ static int socfpga_a10_clk_probe(struct udevice *dev)
plat->regs = pplat->regs;
}
- if (!fdt_node_check_compatible(fdt, offset,
- "altr,socfpga-a10-pll-clock")) {
+ if (ofnode_device_is_compatible(node,
+ "altr,socfpga-a10-pll-clock")) {
/* Main PLL has 3 upstream clock */
if (plat->clks.count == 3)
plat->type = SOCFPGA_A10_CLK_MAIN_PLL;
else
plat->type = SOCFPGA_A10_CLK_PER_PLL;
- } else if (!fdt_node_check_compatible(fdt, offset,
- "altr,socfpga-a10-perip-clk")) {
+ } else if (ofnode_device_is_compatible(node,
+ "altr,socfpga-a10-perip-clk")) {
plat->type = SOCFPGA_A10_CLK_PERIP_CLK;
- } else if (!fdt_node_check_compatible(fdt, offset,
- "altr,socfpga-a10-gate-clk")) {
+ } else if (ofnode_device_is_compatible(node,
+ "altr,socfpga-a10-gate-clk")) {
plat->type = SOCFPGA_A10_CLK_GATE_CLK;
} else {
plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK;
--
2.7.4
