Hi Patrick On 3/31/20 6:04 PM, Patrick Delaunay wrote: > Use the DDR3 dtsi files generated by STM32CubeMX 5.6.0 > Speed Bin Grade = using DDR3-1066G / 8-8-8 and all others > parameters at default value. > > Signed-off-by: Patrick Delaunay <patrick.delau...@st.com> > --- > > .../dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 49 +++++++++---------- > .../dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 49 +++++++++---------- > 2 files changed, 48 insertions(+), 50 deletions(-) > > diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi > b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi > index 11e8f2bef6..c0fc1f772e 100644 > --- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi > +++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi > @@ -1,24 +1,23 @@ > // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause > /* > * Copyright (C) 2018, STMicroelectronics - All Rights Reserved > + */ > + > +/* > + * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs > + * DDR type: DDR3 / DDR3L > + * DDR width: 16bits > + * DDR density: 4Gb > + * System frequency: 533000Khz > + * Relaxed Timing Mode: false > + * Address mapping type: RBC > * > - * STM32MP157C DK1/DK2 BOARD configuration > - * 1x DDR3L 4Gb, 16-bit, 533MHz. > - * Reference used NT5CC256M16DP-DI from NANYA > - * > - * DDR type / Platform DDR3/3L > - * freq 533MHz > - * width 16 > - * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G > - * DDR density 4 > - * timing mode optimized > - * Scheduling/QoS options : type = 2 > - * address mapping : RBC > - * Tc > + 85C : N > + * Save Date: 2020.02.20, save Time: 18:45:20 > */ > -#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45" > -#define DDR_MEM_SPEED 533000 > -#define DDR_MEM_SIZE 0x20000000 > + > +#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz" > +#define DDR_MEM_SPEED 533000 > +#define DDR_MEM_SIZE 0x20000000 > > #define DDR_MSTR 0x00041401 > #define DDR_MRCTRL0 0x00000010 > @@ -50,15 +49,6 @@ > #define DDR_DFIUPD1 0x00000000 > #define DDR_DFIUPD2 0x00000000 > #define DDR_DFIPHYMSTR 0x00000000 > -#define DDR_ADDRMAP1 0x00070707 > -#define DDR_ADDRMAP2 0x00000000 > -#define DDR_ADDRMAP3 0x1F000000 > -#define DDR_ADDRMAP4 0x00001F1F > -#define DDR_ADDRMAP5 0x06060606 > -#define DDR_ADDRMAP6 0x0F060606 > -#define DDR_ADDRMAP9 0x00000000 > -#define DDR_ADDRMAP10 0x00000000 > -#define DDR_ADDRMAP11 0x00000000 > #define DDR_ODTCFG 0x06000600 > #define DDR_ODTMAP 0x00000001 > #define DDR_SCHED 0x00000C01 > @@ -83,6 +73,15 @@ > #define DDR_PCFGQOS1_1 0x00800040 > #define DDR_PCFGWQOS0_1 0x01100C03 > #define DDR_PCFGWQOS1_1 0x01000200 > +#define DDR_ADDRMAP1 0x00070707 > +#define DDR_ADDRMAP2 0x00000000 > +#define DDR_ADDRMAP3 0x1F000000 > +#define DDR_ADDRMAP4 0x00001F1F > +#define DDR_ADDRMAP5 0x06060606 > +#define DDR_ADDRMAP6 0x0F060606 > +#define DDR_ADDRMAP9 0x00000000 > +#define DDR_ADDRMAP10 0x00000000 > +#define DDR_ADDRMAP11 0x00000000 > #define DDR_PGCR 0x01442E02 > #define DDR_PTR0 0x0022AA5B > #define DDR_PTR1 0x04841104 > diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi > b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi > index 4b70b60554..fc226d2544 100644 > --- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi > +++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi > @@ -1,24 +1,23 @@ > // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause > /* > * Copyright (C) 2018, STMicroelectronics - All Rights Reserved > + */ > + > +/* > + * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs > + * DDR type: DDR3 / DDR3L > + * DDR width: 32bits > + * DDR density: 8Gb > + * System frequency: 533000Khz > + * Relaxed Timing Mode: false > + * Address mapping type: RBC > * > - * STM32MP157C ED1 BOARD configuration > - * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology. > - * Reference used NT5CC256M16DP-DI from NANYA > - * > - * DDR type / Platform DDR3/3L > - * freq 533MHz > - * width 32 > - * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G > - * DDR density 8 > - * timing mode optimized > - * Scheduling/QoS options : type = 2 > - * address mapping : RBC > - * Tc > + 85C : N > + * Save Date: 2020.02.20, save Time: 18:49:33 > */ > -#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45" > -#define DDR_MEM_SPEED 533000 > -#define DDR_MEM_SIZE 0x40000000 > + > +#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000Khz" > +#define DDR_MEM_SPEED 533000 > +#define DDR_MEM_SIZE 0x40000000 > > #define DDR_MSTR 0x00040401 > #define DDR_MRCTRL0 0x00000010 > @@ -50,15 +49,6 @@ > #define DDR_DFIUPD1 0x00000000 > #define DDR_DFIUPD2 0x00000000 > #define DDR_DFIPHYMSTR 0x00000000 > -#define DDR_ADDRMAP1 0x00080808 > -#define DDR_ADDRMAP2 0x00000000 > -#define DDR_ADDRMAP3 0x00000000 > -#define DDR_ADDRMAP4 0x00001F1F > -#define DDR_ADDRMAP5 0x07070707 > -#define DDR_ADDRMAP6 0x0F070707 > -#define DDR_ADDRMAP9 0x00000000 > -#define DDR_ADDRMAP10 0x00000000 > -#define DDR_ADDRMAP11 0x00000000 > #define DDR_ODTCFG 0x06000600 > #define DDR_ODTMAP 0x00000001 > #define DDR_SCHED 0x00000C01 > @@ -83,6 +73,15 @@ > #define DDR_PCFGQOS1_1 0x00800040 > #define DDR_PCFGWQOS0_1 0x01100C03 > #define DDR_PCFGWQOS1_1 0x01000200 > +#define DDR_ADDRMAP1 0x00080808 > +#define DDR_ADDRMAP2 0x00000000 > +#define DDR_ADDRMAP3 0x00000000 > +#define DDR_ADDRMAP4 0x00001F1F > +#define DDR_ADDRMAP5 0x07070707 > +#define DDR_ADDRMAP6 0x0F070707 > +#define DDR_ADDRMAP9 0x00000000 > +#define DDR_ADDRMAP10 0x00000000 > +#define DDR_ADDRMAP11 0x00000000 > #define DDR_PGCR 0x01442E02 > #define DDR_PTR0 0x0022AA5B > #define DDR_PTR1 0x04841104
Reviewed-by: Patrice Chotard <patrice.chot...@st.com> Thanks
