Hi Jagan, >-----Original Message----- >From: Jagan Teki <ja...@amarulasolutions.com> >Sent: 07 April 2020 01:00 >To: Pragnesh Patel <pragnesh.pa...@sifive.com> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra ><atish.pa...@wdc.com>; palmerdabb...@google.com; Bin Meng ><bmeng...@gmail.com>; Paul Walmsley <paul.walms...@sifive.com>; Troy >Benjegerdes <troy.benjeger...@sifive.com>; Anup Patel ><anup.pa...@wdc.com>; Sagar Kadam <sagar.ka...@sifive.com>; Rick Chen ><r...@andestech.com> >Subject: Re: [PATCH v6 07/17] sifive: dts: fu540: Add DDR controller and phy >register settings > >[External Email] Do not click links or attachments unless you recognize the >sender and know the content is safe > >On Sun, Mar 29, 2020 at 10:36 PM Pragnesh Patel ><pragnesh.pa...@sifive.com> wrote: >> >> Add DDR controller and phy register settings, taken from fsbl >> (https://github.com/sifive/freedom-u540-c000-bootloader.git) >> >> Signed-off-by: Pragnesh Patel <pragnesh.pa...@sifive.com> >> --- >> arch/riscv/dts/fu540-c000-u-boot.dtsi | 7 + > >separate patch > >> ...fu540-hifive-unleashed-a00-sdram-ddr4.dtsi | 1489 >> +++++++++++++++++ > >separate patch > >> .../dts/hifive-unleashed-a00-u-boot.dtsi | 1 + > >squash with SPL support patch.
Will update all in v7. > >Jagan.
