Fix up some incorrect code style in calls to functions in the linux/time.h
header, mostly udelay().

Signed-off-by: Simon Glass <s...@chromium.org>

---

Changes in v2:
- Split out code-style changes for time functions into a new patch

 arch/arm/cpu/sa1100/timer.c           |  2 +-
 board/sbc8641d/sbc8641d.c             |  8 ++++----
 cmd/mem.c                             |  4 ++--
 drivers/ata/sata_sil3114.c            | 16 ++++++++--------
 drivers/fpga/stratixII.c              |  6 +++---
 drivers/net/ax88180.c                 | 10 +++++-----
 drivers/net/eepro100.c                | 18 +++++++++---------
 drivers/net/lan91c96.c                | 10 +++++-----
 drivers/net/rtl8139.c                 |  6 +++---
 drivers/net/smc91111.c                | 22 +++++++++++-----------
 drivers/qe/uec_phy.c                  |  6 +++---
 drivers/rtc/ds1306.c                  | 26 +++++++++++++-------------
 drivers/video/mb862xx.c               |  6 +++---
 examples/standalone/smc91111_eeprom.c |  6 +++---
 lib/time.c                            |  2 +-
 15 files changed, 74 insertions(+), 74 deletions(-)

diff --git a/arch/arm/cpu/sa1100/timer.c b/arch/arm/cpu/sa1100/timer.c
index 8e20c96bcda..f2cbee5dca7 100644
--- a/arch/arm/cpu/sa1100/timer.c
+++ b/arch/arm/cpu/sa1100/timer.c
@@ -23,7 +23,7 @@ ulong get_timer (ulong base)
        return get_timer_masked ();
 }
 
-void __udelay (unsigned long usec)
+void __udelay(unsigned long usec)
 {
        ulong tmo;
        ulong endtime;
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 2346564c7d0..91867d4f3d2 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -123,12 +123,12 @@ long int fixed_sdram (void)
 
        asm ("sync;isync");
 
-       udelay (500);
+       udelay(500);
 
        ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
        asm ("sync; isync");
 
-       udelay (500);
+       udelay(500);
        ddr = &immap->im_ddr2;
 
        ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
@@ -154,12 +154,12 @@ long int fixed_sdram (void)
 
        asm ("sync;isync");
 
-       udelay (500);
+       udelay(500);
 
        ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
        asm ("sync; isync");
 
-       udelay (500);
+       udelay(500);
 #endif
        return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
diff --git a/cmd/mem.c b/cmd/mem.c
index 13641de63c9..0a5aa8b47cb 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -189,7 +189,7 @@ static int do_mem_mdc(struct cmd_tbl *cmdtp, int flag, int 
argc,
 
                /* delay for <count> ms... */
                for (i=0; i<count; i++)
-                       udelay (1000);
+                       udelay(1000);
 
                /* check for ctrl-c to abort... */
                if (ctrlc()) {
@@ -217,7 +217,7 @@ static int do_mem_mwc(struct cmd_tbl *cmdtp, int flag, int 
argc,
 
                /* delay for <count> ms... */
                for (i=0; i<count; i++)
-                       udelay (1000);
+                       udelay(1000);
 
                /* check for ctrl-c to abort... */
                if (ctrlc()) {
diff --git a/drivers/ata/sata_sil3114.c b/drivers/ata/sata_sil3114.c
index 7e802170d80..7348566dd0b 100644
--- a/drivers/ata/sata_sil3114.c
+++ b/drivers/ata/sata_sil3114.c
@@ -64,9 +64,9 @@ static int sata_bus_softreset (int num)
 
        port[num].ctl_reg = 0x08;       /*Default value of control reg */
        writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
-       udelay (10);
+       udelay(10);
        writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
-       udelay (10);
+       udelay(10);
        writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
 
        /* spec mandates ">= 2ms" before checking status.
@@ -121,7 +121,7 @@ static void sata_identify (int num, int dev)
        cmd = ATA_CMD_ID_ATA;   /*Device Identify Command */
        writeb (cmd, port[num].ioaddr.command_addr);
        readb (port[num].ioaddr.altstatus_addr);
-       udelay (10);
+       udelay(10);
 
        status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000, 0);
        if (status & ATA_ERR) {
@@ -194,7 +194,7 @@ static void set_Feature_cmd (int num, int dev)
        writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
        writeb (ATA_CMD_SET_FEATURES, port[num].ioaddr.command_addr);
 
-       udelay (50);
+       udelay(50);
        msleep (150);
 
        status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
@@ -392,7 +392,7 @@ static u8 wait_for_irq (int num, unsigned int max)
                if (readl (port) & VND_TF_CNST_INTST) {
                        break;
                }
-               udelay (1000);
+               udelay(1000);
                max--;
        } while ((max > 0));
 
@@ -408,7 +408,7 @@ static u8 sata_busy_wait (struct sata_ioports *ioaddr, int 
bits,
                if (!((status = sata_chk_status (ioaddr, usealtstatus)) & 
bits)) {
                        break;
                }
-               udelay (1000);
+               udelay(1000);
                max--;
        } while ((status & bits) && (max > 0));
 
@@ -429,7 +429,7 @@ static void msleep (int count)
        int i;
 
        for (i = 0; i < count; i++)
-               udelay (1000);
+               udelay(1000);
 }
 
 /* Read up to 255 sectors
@@ -616,7 +616,7 @@ ulong sata_write (int device, ulong block, lbaint_t blkcnt, 
const void *buff)
 
                output_data (&port[num].ioaddr, buffer, ATA_SECTOR_WORDS);
                readb (port[num].ioaddr.altstatus_addr);
-               udelay (50);
+               udelay(50);
 
                ++n;
                ++blknr;
diff --git a/drivers/fpga/stratixII.c b/drivers/fpga/stratixII.c
index 12d8dd19bf6..4edbfe4ba87 100644
--- a/drivers/fpga/stratixII.c
+++ b/drivers/fpga/stratixII.c
@@ -116,9 +116,9 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, 
size_t bsize,
 
        /* 2. Strat burn cycle by deasserting config for t_CFG and waiting 
t_CF2CK after reaserted */
        fns->config (0, 1, cookie);
-       udelay (5);             /* nCONFIG low pulse width 2usec */
+       udelay(5);              /* nCONFIG low pulse width 2usec */
        fns->config (1, 1, cookie);
-       udelay (100);           /* nCONFIG high to first rising edge on DCLK */
+       udelay(100);            /* nCONFIG high to first rising edge on DCLK */
 
        /* 3. Start the Data cycle with clk deasserted */
        bytecount = 0;
@@ -168,7 +168,7 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, 
size_t bsize,
 
        /* 4. Set one last clock and check conf done signal */
        fns->clk (1, 1, cookie);
-       udelay (100);
+       udelay(100);
        if (!fns->done (cookie)) {
                printf (" error!.\n");
                fns->abort (cookie);
diff --git a/drivers/net/ax88180.c b/drivers/net/ax88180.c
index d13eb11187c..2715653cd45 100644
--- a/drivers/net/ax88180.c
+++ b/drivers/net/ax88180.c
@@ -118,7 +118,7 @@ static int ax88180_phy_reset (struct eth_device *dev)
 
        /* Wait for the reset to complete, or time out (500 ms) */
        while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) {
-               udelay (1000);
+               udelay(1000);
                if (--delay_cnt == 0) {
                        printf ("Failed to reset PHY!\n");
                        return -1;
@@ -177,7 +177,7 @@ static int ax88180_poll_tx_complete (struct eth_device *dev)
                if ((tmpval & txbs_txdp) == 0)
                        break;
 
-               udelay (100);
+               udelay(100);
        }
 
        if (TimeOutCnt)
@@ -342,7 +342,7 @@ static void ax88180_media_config (struct eth_device *dev)
                if (bmsr_val & BMSR_LSTATUS) {
                        break;
                }
-               udelay (100);
+               udelay(100);
        }
 
        bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
@@ -364,7 +364,7 @@ static void ax88180_media_config (struct eth_device *dev)
                                if (bmsr_val & BMSR_ANEGCOMPLETE) {
                                        break;
                                }
-                               udelay (100);
+                               udelay(100);
                        }
                } else
                        debug ("ax88180: Auto-negotiation is disabled.\n");
@@ -680,7 +680,7 @@ static void ax88180_read_mac_addr (struct eth_device *dev)
                tmp_regval = INW (dev, PROMCTRL);
                if ((tmp_regval & RELOAD_EEPROM) == 0)
                        break;
-               udelay (1000);
+               udelay(1000);
        }
 
        /* Get MAC addresses */
diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c
index 2fe0ba6e20f..36a9d4d91c3 100644
--- a/drivers/net/eepro100.c
+++ b/drivers/net/eepro100.c
@@ -462,7 +462,7 @@ int eepro100_initialize (bd_t * bis)
                 */
                pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
 
-               udelay (10 * 1000);
+               udelay(10 * 1000);
 
                read_hw_addr (dev, bis);
        }
@@ -480,10 +480,10 @@ static int eepro100_init (struct eth_device *dev, bd_t * 
bis)
        /* Reset the ethernet controller
         */
        OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
-       udelay (20);
+       udelay(20);
 
        OUTL (dev, I82559_RESET, SCBPort);
-       udelay (20);
+       udelay(20);
 
        if (!wait_for_eepro100 (dev)) {
                printf ("Error: Can not reset ethernet controller.\n");
@@ -721,10 +721,10 @@ static void eepro100_halt (struct eth_device *dev)
        /* Reset the ethernet controller
         */
        OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
-       udelay (20);
+       udelay(20);
 
        OUTL (dev, I82559_RESET, SCBPort);
-       udelay (20);
+       udelay(20);
 
        if (!wait_for_eepro100 (dev)) {
                printf ("Error: Can not reset ethernet controller.\n");
@@ -760,19 +760,19 @@ static int read_eeprom (struct eth_device *dev, int 
location, int addr_len)
                short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
 
                OUTW (dev, EE_ENB | dataval, SCBeeprom);
-               udelay (1);
+               udelay(1);
                OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
-               udelay (1);
+               udelay(1);
        }
        OUTW (dev, EE_ENB, SCBeeprom);
 
        for (i = 15; i >= 0; i--) {
                OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
-               udelay (1);
+               udelay(1);
                retval = (retval << 1) |
                                ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
                OUTW (dev, EE_ENB, SCBeeprom);
-               udelay (1);
+               udelay(1);
        }
 
        /* Terminate the EEPROM access. */
diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c
index c08bd21f95a..1989b66a486 100644
--- a/drivers/net/lan91c96.c
+++ b/drivers/net/lan91c96.c
@@ -211,7 +211,7 @@ static void smc_reset(struct eth_device *dev)
        SMC_SELECT_BANK(dev, 0);
        SMC_outw(dev, LAN91C96_RCR_SOFT_RST, LAN91C96_RCR);
 
-       udelay (10);
+       udelay(10);
 
        /* Disable transmit and receive functionality */
        SMC_outw(dev, 0, LAN91C96_RCR);
@@ -438,7 +438,7 @@ static int smc_send_packet(struct eth_device *dev, void 
*packet,
 
                /* wait for MMU getting ready (low) */
                while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
-                       udelay (10);
+                       udelay(10);
 
                PRINTK2("MMU ready\n");
 
@@ -455,7 +455,7 @@ static int smc_send_packet(struct eth_device *dev, void 
*packet,
 
                /* wait for MMU getting ready (low) */
                while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
-                       udelay (10);
+                       udelay(10);
 
                PRINTK2 ("MMU ready\n");
        }
@@ -600,13 +600,13 @@ static int smc_rcv(struct eth_device *dev)
        }
 
        while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
-               udelay (1);             /* Wait until not busy */
+               udelay(1);              /* Wait until not busy */
 
        /*  error or good, tell the card to get rid of this packet */
        SMC_outw(dev, LAN91C96_MMUCR_RELEASE_RX, LAN91C96_MMU);
 
        while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
-               udelay (1);             /* Wait until not busy */
+               udelay(1);              /* Wait until not busy */
 
        if (!is_error) {
                /* Pass the packet up to the protocol layers. */
diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c
index 67be1a3dc3f..b8c402270ab 100644
--- a/drivers/net/rtl8139.c
+++ b/drivers/net/rtl8139.c
@@ -237,7 +237,7 @@ int rtl8139_initialize(bd_t *bis)
 
                pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
 
-               udelay (10 * 1000);
+               udelay(10 * 1000);
        }
 
        return card_number;
@@ -357,7 +357,7 @@ static void rtl_reset(struct eth_device *dev)
        /* Give the chip 10ms to finish the reset. */
        for (i=0; i<100; ++i){
                if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
-               udelay (100); /* wait 100us */
+               udelay(100); /* wait 100us */
        }
 
 
@@ -528,6 +528,6 @@ static void rtl_disable(struct eth_device *dev)
        /* Give the chip 10ms to finish the reset. */
        for (i=0; i<100; ++i){
                if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
-               udelay (100); /* wait 100us */
+               udelay(100); /* wait 100us */
        }
 }
diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c
index 5754c3106c9..52bbf05a1e0 100644
--- a/drivers/net/smc91111.c
+++ b/drivers/net/smc91111.c
@@ -266,7 +266,7 @@ static inline void smc_wait_mmu_release_complete (struct 
eth_device *dev)
 
        /* assume bank 2 selected */
        while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
-               udelay (1);     /* Wait until not busy */
+               udelay(1);      /* Wait until not busy */
                if (++count > 200)
                        break;
        }
@@ -318,7 +318,7 @@ static void smc_reset (struct eth_device *dev)
        SMC_SELECT_BANK (dev, 0);
 
        /* this should pause enough for the chip to be happy */
-       udelay (10);
+       udelay(10);
 
        /* Disable transmit and receive functionality */
        SMC_outw (dev, RCR_CLEAR, RCR_REG);
@@ -333,7 +333,7 @@ static void smc_reset (struct eth_device *dev)
        smc_wait_mmu_release_complete (dev);
        SMC_outw (dev, MC_RESET, MMU_CMD_REG);
        while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
-               udelay (1);     /* Wait until not busy */
+               udelay(1);      /* Wait until not busy */
 
        /* Note:  It doesn't seem that waiting for the MMU busy is needed here,
           but this is a place where future chipsets _COULD_ break.  Be wary
@@ -564,7 +564,7 @@ again:
 
                /* wait for MMU getting ready (low) */
                while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
-                       udelay (10);
+                       udelay(10);
                }
 
                PRINTK2 ("MMU ready\n");
@@ -583,7 +583,7 @@ again:
 
                /* wait for MMU getting ready (low) */
                while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
-                       udelay (10);
+                       udelay(10);
                }
 
                PRINTK2 ("MMU ready\n");
@@ -957,19 +957,19 @@ static word smc_read_phy_register (struct eth_device 
*dev, byte phyreg)
        for (i = 0; i < sizeof bits; ++i) {
                /* Clock Low - output data */
                SMC_outw (dev, mii_reg | bits[i], MII_REG);
-               udelay (SMC_PHY_CLOCK_DELAY);
+               udelay(SMC_PHY_CLOCK_DELAY);
 
 
                /* Clock Hi - input data */
                SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
-               udelay (SMC_PHY_CLOCK_DELAY);
+               udelay(SMC_PHY_CLOCK_DELAY);
                bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
        }
 
        /* Return to idle state */
        /* Set clock to low, data to low, and output tristated */
        SMC_outw (dev, mii_reg, MII_REG);
-       udelay (SMC_PHY_CLOCK_DELAY);
+       udelay(SMC_PHY_CLOCK_DELAY);
 
        /* Restore original bank select */
        SMC_SELECT_BANK (dev, oldBank);
@@ -1078,19 +1078,19 @@ static void smc_write_phy_register (struct eth_device 
*dev, byte phyreg,
        for (i = 0; i < sizeof bits; ++i) {
                /* Clock Low - output data */
                SMC_outw (dev, mii_reg | bits[i], MII_REG);
-               udelay (SMC_PHY_CLOCK_DELAY);
+               udelay(SMC_PHY_CLOCK_DELAY);
 
 
                /* Clock Hi - input data */
                SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
-               udelay (SMC_PHY_CLOCK_DELAY);
+               udelay(SMC_PHY_CLOCK_DELAY);
                bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
        }
 
        /* Return to idle state */
        /* Set clock to low, data to low, and output tristated */
        SMC_outw (dev, mii_reg, MII_REG);
-       udelay (SMC_PHY_CLOCK_DELAY);
+       udelay(SMC_PHY_CLOCK_DELAY);
 
        /* Restore original bank select */
        SMC_SELECT_BANK (dev, oldBank);
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index 94253797946..1dae2615095 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -875,7 +875,7 @@ void marvell_phy_interface_mode(struct eth_device *dev, 
phy_interface_t type,
                        uec_phy_write(mii_info, 0x04, 0x01e1);
                        uec_phy_write(mii_info, 0x00, 0x9140);
                        uec_phy_write(mii_info, 0x00, 0x1000);
-                       udelay (100000);
+                       mdelay(100);
                        uec_phy_write(mii_info, 0x00, 0x2900);
                        uec_phy_write(mii_info, 0x14, 0x0cd2);
                        uec_phy_write(mii_info, 0x00, 0xa100);
@@ -884,13 +884,13 @@ void marvell_phy_interface_mode(struct eth_device *dev, 
phy_interface_t type,
                        uec_phy_write(mii_info, 0x04, 0x05e1);
                        uec_phy_write(mii_info, 0x00, 0xa100);
                        uec_phy_write(mii_info, 0x00, 0x2100);
-                       udelay (1000000);
+                       mdelay(1000);
                } else if (speed == SPEED_10) {
                        uec_phy_write(mii_info, 0x14, 0x8e40);
                        uec_phy_write(mii_info, 0x1b, 0x800b);
                        uec_phy_write(mii_info, 0x14, 0x0c82);
                        uec_phy_write(mii_info, 0x00, 0x8100);
-                       udelay (1000000);
+                       mdelay(1000);
                }
        }
 
diff --git a/drivers/rtc/ds1306.c b/drivers/rtc/ds1306.c
index 02d617e09c9..1bd1151e1b3 100644
--- a/drivers/rtc/ds1306.c
+++ b/drivers/rtc/ds1306.c
@@ -71,7 +71,7 @@ int rtc_get (struct rtc_time *tmp)
 
        /* Now we can enable the DS1306 RTC */
        immap->im_cpm.cp_pbdat |= PB_SPI_CE;
-       udelay (10);
+       udelay(10);
 
        /* Shift out the address (0) of the time in the Clock Chip */
        soft_spi_send (0);
@@ -105,7 +105,7 @@ int rtc_get (struct rtc_time *tmp)
 
        /* Now we can disable the DS1306 RTC */
        immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;   /* Disable DS1306 Chip */
-       udelay (10);
+       udelay(10);
 
        rtc_calc_weekday(tmp);  /* Determine the day of week */
 
@@ -127,7 +127,7 @@ int rtc_set (struct rtc_time *tmp)
 
        /* Now we can enable the DS1306 RTC */
        immap->im_cpm.cp_pbdat |= PB_SPI_CE;    /* Enable DS1306 Chip */
-       udelay (10);
+       udelay(10);
 
        /* First disable write protect in the clock chip control register */
        soft_spi_send (0x8F);   /* send address of the control register */
@@ -135,11 +135,11 @@ int rtc_set (struct rtc_time *tmp)
 
        /* Now disable the DS1306 to terminate the write */
        immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;
-       udelay (10);
+       udelay(10);
 
        /* Now enable the DS1306 to initiate a new write */
        immap->im_cpm.cp_pbdat |= PB_SPI_CE;
-       udelay (10);
+       udelay(10);
 
        /* Next, send the address of the clock time write registers */
        soft_spi_send (0x80);   /* send address of the first time register */
@@ -156,11 +156,11 @@ int rtc_set (struct rtc_time *tmp)
 
        /* Now we can disable the Clock chip to terminate the burst write */
        immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;   /* Disable DS1306 Chip */
-       udelay (10);
+       udelay(10);
 
        /* Now we can enable the Clock chip to initiate a new write */
        immap->im_cpm.cp_pbdat |= PB_SPI_CE;    /* Enable DS1306 Chip */
-       udelay (10);
+       udelay(10);
 
        /* First we Enable write protect in the clock chip control register */
        soft_spi_send (0x8F);   /* send address of the control register */
@@ -168,7 +168,7 @@ int rtc_set (struct rtc_time *tmp)
 
        /* Now disable the DS1306 */
        immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;   /*  Disable DS1306 Chip */
-       udelay (10);
+       udelay(10);
 
        /* Set standard MPC8xx clock to the same time so Linux will
         * see the time even if it doesn't have a DS1306 clock driver.
@@ -204,7 +204,7 @@ static void init_spi (void)
        immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK);
 
        immap->im_cpm.cp_pbdir &= ~PB_SPIMISO;  /* Make MISO pin an input */
-       udelay (10);
+       udelay(10);
 }
 
 /* ------------------------------------------------------------------------- */
@@ -227,10 +227,10 @@ static void soft_spi_send (unsigned char n)
                        immap->im_cpm.cp_pbdat |= PB_SPIMOSI;   /* Set MOSI to 
1 */
                else
                        immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI;  /* Set MOSI to 
0 */
-               udelay (10);
+               udelay(10);
 
                immap->im_cpm.cp_pbdat &= ~PB_SPISCK;   /* Lower SCK */
-               udelay (10);
+               udelay(10);
 
                bitpos >>= 1;   /* Shift for next bit position */
        }
@@ -253,11 +253,11 @@ static unsigned char soft_spi_read (void)
        /* Read 8 bits here */
        for (i = 0; i < 8; i++) {       /* Do 8 bits in loop */
                immap->im_cpm.cp_pbdat |= PB_SPISCK;    /* Raise SCK */
-               udelay (10);
+               udelay(10);
                if (immap->im_cpm.cp_pbdat & PB_SPIMISO)        /* Get a bit of 
data */
                        spi_byte |= bitpos;     /* Set data accordingly */
                immap->im_cpm.cp_pbdat &= ~PB_SPISCK;   /* Lower SCK */
-               udelay (10);
+               udelay(10);
                bitpos >>= 1;   /* Shift for next bit position */
        }
 
diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c
index 301c1f0df17..a3a7a8dd98d 100644
--- a/drivers/video/mb862xx.c
+++ b/drivers/video/mb862xx.c
@@ -79,7 +79,7 @@ static void gdc_sw_reset (void)
        GraphicDevice *dev = &mb862xx;
 
        HOST_WR_REG (GC_SRST, 0x1);
-       udelay (500);
+       udelay(500);
        video_hw_init ();
 }
 
@@ -222,9 +222,9 @@ unsigned int pci_video_init (void)
 
        /* Setup clocks and memory mode for Coral-P(A) */
        HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF);
-       udelay (200);
+       udelay(200);
        HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR);
-       udelay (100);
+       udelay(100);
        return dev->frameAdrs;
 }
 
diff --git a/examples/standalone/smc91111_eeprom.c 
b/examples/standalone/smc91111_eeprom.c
index a43d14f3967..631b1b04d6f 100644
--- a/examples/standalone/smc91111_eeprom.c
+++ b/examples/standalone/smc91111_eeprom.c
@@ -237,7 +237,7 @@ void copy_from_eeprom (struct eth_device *dev)
                CTL_RELOAD, CTL_REG);
        i = 100;
        while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --i)
-               udelay (100);
+               udelay(100);
        if (i == 0) {
                printf ("Timeout Refreshing EEPROM registers\n");
        } else {
@@ -318,7 +318,7 @@ int read_eeprom_reg (struct eth_device *dev, int reg)
                CTL_RELOAD, CTL_REG);
        timeout = 100;
        while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout)
-               udelay (100);
+               udelay(100);
        if (timeout == 0) {
                printf ("Timeout Reading EEPROM register %02x\n", reg);
                return 0;
@@ -341,7 +341,7 @@ int write_eeprom_reg (struct eth_device *dev, int value, 
int reg)
                CTL_STORE, CTL_REG);
        timeout = 100;
        while ((SMC_inw (dev, CTL_REG) & CTL_STORE) && --timeout)
-               udelay (100);
+               udelay(100);
        if (timeout == 0) {
                printf ("Timeout Writing EEPROM register %02x\n", reg);
                return 0;
diff --git a/lib/time.c b/lib/time.c
index 3d6447d7c0a..551698e36d0 100644
--- a/lib/time.c
+++ b/lib/time.c
@@ -183,7 +183,7 @@ void udelay(unsigned long usec)
        do {
                WATCHDOG_RESET();
                kv = usec > CONFIG_WD_PERIOD ? CONFIG_WD_PERIOD : usec;
-               __udelay (kv);
+               __udelay(kv);
                usec -= kv;
        } while(usec);
 }
-- 
2.26.0.110.g2183baf09c-goog

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