On 4/9/20 8:10 PM, Patrick DELAUNAY wrote: > Dear Marek, > >> From: Marek Vasut <ma...@denx.de> >> Sent: vendredi 3 avril 2020 23:33 >> >> On 4/3/20 11:25 AM, Patrick Delaunay wrote: >>> Activate cache on DDR to improves the accesses to DDR used by SPL: >>> - CONFIG_SPL_BSS_START_ADDR >>> - CONFIG_SYS_SPL_MALLOC_START >>> >>> Cache is configured only when DDR is fully initialized, to avoid >>> speculative access and issue in get_ram_size(). >>> Data cache is deactivated at the end of SPL, to flush the data cache >>> and the TLB. >>> >>> Signed-off-by: Patrick Delaunay <patrick.delau...@st.com> >>> --- >>> >>> Changes in v2: >>> - new >>> > > [...] > >>> +void spl_board_prepare_for_boot(void) { >>> + dcache_disable(); >>> + debug("SPL bye\n"); >>> +} >>> + >>> +void spl_board_prepare_for_boot_linux(void) >>> +{ >>> + dcache_disable(); >>> + debug("SPL bye\n"); >> >> Is the debug() statement really needed ? I think the common SPL code already >> has some. > > Not needed, I will drop them in V3.
Thanks