Register value table for DDR PHY clock divider are wrong. They should be
0 or 1 for divide-by-2 or divide-by-4, respectively. Not 1 or 2. Current
values do not make sense, since 2 cannot be achieved, because the
register is only 1 bit long (mask is set to 1).
This fixes clk dump reporting DDR PHY clock rate differently from Linux.
Signed-off-by: Marek Behún <marek.be...@nic.cz>
---
drivers/clk/mvebu/armada-37xx-periph.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c
b/drivers/clk/mvebu/armada-37xx-periph.c
index 068e48ea04..855f979b4f 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -89,8 +89,8 @@ static const struct clk_div_table div_table1[] = {
};
static const struct clk_div_table div_table2[] = {
- { 2, 1 },
- { 4, 2 },
+ { 2, 0 },
+ { 4, 1 },
{ 0, 0 },
};
--
2.24.1
