On Tue, Apr 21, 2020 at 12:49 PM Vignesh Raghavendra <vigne...@ti.com> wrote: > > Hi Jagan, > > On 20/04/20 5:39 pm, Jagan Teki wrote: > > Some of the SPI controllers have a special set of format > > registers that defines how the transfer initiated to the > > FIFO by means of I/O protocol lines. > > > > Each mode of transfer from slave would be required to configure > > the I/O protocol lines so-that the master would identify how > > many number I/O protocol lines were used and alter the protocol > > bits on the controller. > > > > To address this issue (on these kinds of SPI controllers) this > > series is trying to send the I/O protocol lines being used > > on particular transfers. > > > > patch 1: Transfer the opcode alone > > Has this been tested on more than one SPI controller? Is this safe to do?
Yes. Well it is the proper way for handling all types of use cases (like Linux tx/rx_nbits does). > > > > > patch 2: Add SPI I/O protocol lines via spi->proto > > > > patch 3: Use spi->proto on SiFive SPI controller > > > > Any inputs? > > Why cannot SiFive SPI controller implement spi_mem_ops? Is there a non > flash SPI device that supports quad mode? Adding this generic code in spi-mem looks like adding generic code to work for the sake of this controller. Eventually two code bases do the same job with some buswidth extension. Lets hold for some time for testing other boards. Jagan.
