Hi Simon, On Mon, Apr 6, 2020 at 7:22 AM Simon Glass <s...@chromium.org> wrote: > > Add a build for running 64-bit U-Boot from coreboot (which is 32-bit). > This uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot. > > Coreboot boots into SPL and then SPL boots into U-Boot. > > This allows running 64-bit EFI images on x86. > Signed-off-by: Simon Glass <s...@chromium.org> > --- > > board/coreboot/coreboot/MAINTAINERS | 7 +++++ > configs/coreboot64_defconfig | 48 +++++++++++++++++++++++++++++ > doc/board/coreboot/coreboot.rst | 10 ++++++ > 3 files changed, 65 insertions(+) > create mode 100644 configs/coreboot64_defconfig > > diff --git a/board/coreboot/coreboot/MAINTAINERS > b/board/coreboot/coreboot/MAINTAINERS > index 188906b0803..a05673bb0be 100644 > --- a/board/coreboot/coreboot/MAINTAINERS > +++ b/board/coreboot/coreboot/MAINTAINERS > @@ -4,3 +4,10 @@ S: Maintained > F: board/coreboot/coreboot/ > F: include/configs/chromebook_link.h > F: configs/coreboot_defconfig > + > +COREBOOT64 BOARD > +M: Simon Glass <s...@chromium.org> > +S: Maintained > +F: board/coreboot/coreboot/ > +F: include/configs/chromebook_link.h > +F: configs/coreboot64_defconfig > diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig > new file mode 100644 > index 00000000000..80353b8eb36 > --- /dev/null > +++ b/configs/coreboot64_defconfig > @@ -0,0 +1,48 @@ > +CONFIG_X86=y > +CONFIG_SYS_TEXT_BASE=0x1120000 > +CONFIG_ENV_SIZE=0x1000 > +CONFIG_NR_DRAM_BANKS=8 > +CONFIG_PRE_CON_BUF_ADDR=0x100000 > +CONFIG_X86_RUN_64BIT=y > +CONFIG_VENDOR_COREBOOT=y > +CONFIG_TARGET_COREBOOT=y > +CONFIG_SPL_TEXT_BASE=0x1110000 > +CONFIG_FIT=y > +CONFIG_FIT_SIGNATURE=y > +CONFIG_SHOW_BOOT_PROGRESS=y > +CONFIG_USE_BOOTARGS=y > +CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" > +CONFIG_PRE_CONSOLE_BUFFER=y > +CONFIG_SYS_CONSOLE_INFO_QUIET=y > +CONFIG_DISPLAY_BOARDINFO_LATE=y > +CONFIG_LAST_STAGE_INIT=y > +CONFIG_HUSH_PARSER=y > +CONFIG_CMD_IDE=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_PART=y > +CONFIG_CMD_USB=y > +# CONFIG_CMD_SETEXPR is not set > +CONFIG_CMD_DHCP=y > +# CONFIG_CMD_NFS is not set > +CONFIG_CMD_PING=y > +CONFIG_CMD_TIME=y > +CONFIG_CMD_SOUND=y > +CONFIG_CMD_EXT2=y > +CONFIG_CMD_EXT4=y > +CONFIG_CMD_EXT4_WRITE=y > +CONFIG_CMD_FAT=y > +CONFIG_CMD_FS_GENERIC=y > +CONFIG_MAC_PARTITION=y > +# CONFIG_SPL_MAC_PARTITION is not set > +# CONFIG_SPL_DOS_PARTITION is not set > +CONFIG_ISO_PARTITION=y > +CONFIG_EFI_PARTITION=y > +# CONFIG_SPL_EFI_PARTITION is not set > +CONFIG_DEFAULT_DEVICE_TREE="coreboot" > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > +CONFIG_REGMAP=y > +CONFIG_SYSCON=y > +# CONFIG_PCI_PNP is not set > +CONFIG_SOUND=y > +CONFIG_SOUND_I8254=y > +CONFIG_CONSOLE_SCROLL_LINES=5 > diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst > index fd974229eb4..9c44c025a48 100644 > --- a/doc/board/coreboot/coreboot.rst > +++ b/doc/board/coreboot/coreboot.rst > @@ -40,3 +40,13 @@ To enable video you must enable these options in coreboot: > At present it seems that for Minnowboard Max, coreboot does not pass through > the video information correctly (it always says the resolution is 0x0). This > works correctly for link though. > + > +64-bit U-Boot > +------------- > + > +In addition to the 32-bit 'coreboot' build there is a 'coreboot64' build. > This > +produces an image which can be booted from coreboot (32-bit). Internally it > +works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It > +can be useful for running UEFI applications, for example. > + > +This has only been lightly tested. > --
I tested this with QEMU, but it reboots at U-Boot proper: $ qemu-system-x86_64 -nographic -m 2G -bios coreboot.rom Jumping to boot code at 01110000(7ffd5000) U-Boot SPL 2020.04-00376-g785560e (Apr 23 2020 - 15:50:17 +0800) CPU: x86_64, vendor AMD, device 663h Trying to boot from SPI Jumping to 64-bit U-Boot: Note many features are missing U-Boot 2020.04-00376-g785560e (Apr 23 2020 - 15:50:17 +0800) CPU: x86_64, vendor <invalid cpu vendor>, device 0h DRAM: 2 GiB coreboot-4.8.1-dirty Wed May 16 19:00:17 UTC 2018 romstage starting... CBMEM: Regards, Bin Regards, Bin