> From: Jagan Teki <ja...@amarulasolutions.com>
> Date: Sat, 25 Apr 2020 16:33:49 +0530
>
> Add PCIE_PHY clock enablement support on rk3399
> clock driver.
>
> This clock is enabled by default, so do nothing
> if it triggers during the PCIe PHY probe other
> PHY users on this clock will simply fail.
This breaks Ethernet on my firefly-rk3399, and I suspect it does the
same on other boards:
In: serial@ff1a0000
Out: serial@ff1a0000
Err: serial@ff1a0000
Model: Firefly-RK3399 Board
Net: failed to enable clock 0
No ethernet found.
Looking at the px30 clock driver, I think you need to add a few more
clocks here:
SCLK_MAC,
SCLK_MAC_RX,
SCLK_MAC_TX,
SCLK_MACREF,
SCLK_MACREF_OUT,
ACLK_GMAC,
PCLK_GMAC
That makes it work again for me.
Cheers,
Mark
> Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
> ---
> drivers/clk/rockchip/clk_rk3399.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c
> b/drivers/clk/rockchip/clk_rk3399.c
> index d822acace1..8e069fbade 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -1071,12 +1071,27 @@ static int __maybe_unused
> rk3399_clk_set_parent(struct clk *clk,
> return -ENOENT;
> }
>
> +static int rk3399_clk_enable(struct clk *clk)
> +{
> + switch (clk->id) {
> + case SCLK_PCIEPHY_REF:
> + /* do nothing, clk is enabled by default */
> + break;
> + default:
> + debug("%s: unsupported clk %ld\n", __func__, clk->id);
> + return -ENOENT;
> + }
> +
> + return 0;
> +}
> +
> static struct clk_ops rk3399_clk_ops = {
> .get_rate = rk3399_clk_get_rate,
> .set_rate = rk3399_clk_set_rate,
> #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
> .set_parent = rk3399_clk_set_parent,
> #endif
> + .enable = rk3399_clk_enable,
> };
>
> #ifdef CONFIG_SPL_BUILD
> --
> 2.17.1
>
>
