On Fri, 2020-04-24 at 18:50 +0200, Sylwester Nawrocki wrote: > There might be hardware configurations where 64-bit data accesses > to XHCI registers are not supported properly. This patch removes > the readq/writeq so always two 32-bit accesses are used to read/write > 64-bit XHCI registers, similarly as it is done in Linux kernel. > > This patch fixes operation of the XHCI controller on RPI4 Broadcom > BCM2711 SoC based board, where the VL805 USB XHCI controller is > connected to the PCIe Root Complex, which is attached to the system > through the SCB bridge. > > Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely > the 64-bit wide register accesses initiated by the CPU are not properly > translated to a sequence of 32-bit PCIe accesses. > xhci_readq(), for example, always returns same value in upper and lower > 32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234. > > Cc: Sergey Temerkhanov <s.temerkha...@gmail.com> > Signed-off-by: Sylwester Nawrocki <s.nawro...@samsung.com> > --- > Changes since RFC: > - dropped Kconfig option, switched to not using readq/writeq > unconditionally.
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulie...@suse.de> Regards, Nicolas
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