> Subject: RE: [PATCH 2/6] arm: dts: lx2160aqds: add MDIO slots
>
> >-----Original Message-----
> >From: U-Boot <u-boot-boun...@lists.denx.de> On Behalf Of Ioana Ciornei
> >Sent: Wednesday, April 22, 2020 10:39 PM
> >To: Priyanka Jain <priyanka.j...@nxp.com>; u-boot@lists.denx.de
> >Cc: Alexandru Marginean <alexandru.margin...@nxp.com>; Madalin Bucur
> ><madalin.bu...@nxp.com>; Florin Laurentiu Chiculita
> ><florinlaurentiu.chicul...@nxp.com>; Razvan Ionut Cirjan
> ><razvanionut.cir...@nxp.com>; Ioana Ciornei <ioana.cior...@nxp.com>
> >Subject: [PATCH 2/6] arm: dts: lx2160aqds: add MDIO slots
>
> Slot if hardware term. Please mention summary of nodes you adding.
>
I am not sure I get what you are suggesting.
There are multiple HW slots on the LX2160AQDS board.
> >
> >The LX2160A processor has two external MDIO interfaces, described in
> >the DTS as emdio1 and emdio2. EMDIO1 is used with two onboard RGMII
> >PHYs
>
> Board details are now getting detailed, please mention board , may be
> something like On LX2160AQDS, EMDIO1 is used ....
>
Sure.
> >(Realtek RTL8211FD-CG), as well as eight input/output connectors for
> >mezzanine cards. Configuration signals from the Qixis FPGA control the
> >routing of the external MDIOs.
> >
> >Describe register 0x54 of the Qixis FPGA as a MDIO mux controlled over
> >i2c and add its child MDIO busses describing the IO SLOTs.
> Please re-phrase, not able to understand sp mistake : busses
> >
> With this description, requirements are clear, but do also provide details of
> patch changes Like Add nodes of ....
Sure.
> >Signed-off-by: Ioana Ciornei <ioana.cior...@nxp.com>
> >---
> > arch/arm/dts/fsl-lx2160a-qds.dts | 115 ++++++++++++++++++++++++++++++-
> > 1 file changed, 114 insertions(+), 1 deletion(-)
> >
> >diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts
> >b/arch/arm/dts/fsl-lx2160a- qds.dts index 592fd5977e27..4946ce8dfba8
> >100644
> >--- a/arch/arm/dts/fsl-lx2160a-qds.dts
> >+++ b/arch/arm/dts/fsl-lx2160a-qds.dts
> >@@ -2,7 +2,7 @@
> > /*
> > * NXP LX2160AQDS device tree source
> > *
> >- * Copyright 2018-2019 NXP
> >+ * Copyright 2018-2020 NXP
> > *
> > */
> >
> >@@ -18,6 +18,26 @@
> > };
> > };
> >
> >+&dpmac17 {
> >+ status = "okay";
> >+ phy-handle = <&rgmii_phy1>;
> >+ phy-connection-type = "rgmii-id";
> >+};
> >+
> >+&dpmac18 {
> >+ status = "okay";
> >+ phy-handle = <&rgmii_phy2>;
> >+ phy-connection-type = "rgmii-id";
> >+};
> >+
> >+&emdio1 {
> >+ status = "okay";
> >+};
> >+
> >+&emdio2 {
> >+ status = "okay";
> >+};
> >+
> > &esdhc0 {
> > status = "okay";
> > };
> >@@ -30,6 +50,99 @@
> > status = "okay";
> > u-boot,dm-pre-reloc;
> >
> >+ fpga@66 {
> >+ #address-cells = <1>;
> >+ #size-cells = <0>;
> >+ compatible = "simple-mfd";
> >+ reg = <0x66>;
> >+
> >+ mux-mdio@54 {
> >+ #address-cells = <1>;
> >+ #size-cells = <0>;
> >+ compatible = "mdio-mux-i2creg";
> >+ reg = <0x54>;
> >+ #mux-control-cells = <1>;
> >+ mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3
> >+ mdio-parent-bus = <&emdio1>;
> >+
> >+ mdio@00 {
> >+ #address-cells = <1>;
> >+ #size-cells = <0>;
> >+ reg = <0x00>;
> >+
> >+ rgmii_phy1: ethernet-phy@1 {
> >+ reg = <0x1>;
> >+ };
> >+ };
> >+ mdio@08 {
> >+ #address-cells = <1>;
> >+ #size-cells = <0>;
> >+ reg = <0x40>;
> >+
> >+ rgmii_phy2: ethernet-phy@2 {
> >+ reg = <0x2>;
> >+ };
> >+ };
> >+
> >+ emdio1_slot1: mdio@c0 { /* I/O Slot #1 */
> >+ reg = <0xC0>;
> >+ device-name = "emdio1_slot1";
> >+ #address-cells = <1>;
> >+ #size-cells = <0>;
> >+ };
> >+
> >+ emdio1_slot2: mdio@c8 { /* I/O Slot #2 */
> >+ reg = <0xC8>;
> >+ device-name = "emdio1_slot2";
> >+ #address-cells = <1>;
> >+ #size-cells = <0>;
> >+ };
> >+
> >+ emdio1_slot3: mdio@d0 { /* I/O Slot #3 */
> >+ reg = <0xD0>;
> >+ device-name = "emdio1_slot3";
> >+ #address-cells = <1>;
> >+ #size-cells = <0>;
> >+ };
> >+
> >+ emdio1_slot4: mdio@d8 { /* I/O Slot #4 */
> >+ reg = <0xD8>;
> >+ device-name = "emdio1_slot4";
> >+ #address-cells = <1>;
> >+ #size-cells = <0>;
> >+ };
> >+
> >+ emdio1_slot5: mdio@e0 { /* I/O Slot #5 */
> >+ reg = <0xE0>;
> >+ device-name = "emdio1_slot5";
> >+ #address-cells = <1>;
> >+ #size-cells = <0>;
> >+ };
> >+
> >+ emdio1_slot6: mdio@e8 { /* I/O Slot #6 */
> >+ reg = <0xE8>;
> >+ device-name = "emdio1_slot6";
> >+ #address-cells = <1>;
> >+ #size-cells = <0>;
> >+ };
> >+
> >+ emdio1_slot7: mdio@f0 { /* I/O Slot #7 */
> >+ reg = <0xF0>;
> >+ device-name = "emdio1_slot7";
> >+ #address-cells = <1>;
> >+ #size-cells = <0>;
> >+ };
> >+
> >+ emdio1_slot8: mdio@f8 { /* I/O Slot #8 */
> >+ reg = <0xF8>;
> >+ device-name = "emdio1_slot8";
> >+ #address-cells = <1>;
> >+ #size-cells = <0>;
> >+ };
> >+ };
> >+
> >+ };
> >+
> > i2c-mux@77 {
> > compatible = "nxp,pca9547";
> > reg = <0x77>;
> >--
> >2.17.1
>
> Regards
> Priyanka
