V4 = cosmetic update of the previous serie V3 "arm: stm32mp1: activate data cache in SPL and before relocation" http://patchwork.ozlabs.org/project/uboot/list/?series=172557
This serie depends on the ARM cache serie: "arm: caches: allow to activate dcache in SPL and in U-Boot pre-reloc" http://patchwork.ozlabs.org/project/uboot/list/?series=172555 I move tlb in .data section and simplify the implementation by reusing the default weak function dram_bank_mmu_setup() for MMU configuration and mmu_set_region_dcache_behaviour() to setup the specific behavior. I also activate data cache on DDR for SPL. For information the gain of the second patch is limited (few ms) for boot from SDCARD: the SDMMC IP use internal DMA and data cache on DDR is not really used. Gain should be better for other boot use-case. Example of bootstage report on STM32MP157C-DK2, boot from SD card. 1/ For trusted boot chain with TF-A a) Before STM32MP> bootstage report Timer summary in microseconds (9 records): Mark Elapsed Stage 0 0 reset 583,290 583,290 board_init_f 2,348,898 1,765,608 board_init_r 2,664,580 315,682 id=64 2,704,027 39,447 id=65 2,704,729 702 main_loop 5,563,519 2,858,790 id=175 Accumulated time: 41,696 dm_r 615,561 dm_f b) After the serie STM32MP> bootstage report Timer summary in microseconds (9 records): Mark Elapsed Stage 0 0 reset 583,401 583,401 board_init_f 727,725 144,324 board_init_r 1,043,362 315,637 id=64 1,082,806 39,444 id=65 1,083,507 701 main_loop 3,680,827 2,597,320 id=175 Accumulated time: 36,047 dm_f 41,718 dm_r 2/ And for the basic boot chain with SPL a) Before: STM32MP> bootstage report Timer summary in microseconds (12 records): Mark Elapsed Stage 0 0 reset 195,613 195,613 SPL 837,867 642,254 end SPL 840,117 2,250 board_init_f 2,739,639 1,899,522 board_init_r 3,066,815 327,176 id=64 3,103,377 36,562 id=65 3,104,078 701 main_loop 3,142,171 38,093 id=175 Accumulated time: 38,124 dm_spl 41,956 dm_r 648,861 dm_f b) After the serie STM32MP> bootstage report Timer summary in microseconds (12 records): Mark Elapsed Stage 0 0 reset 195,859 195,859 SPL 330,190 134,331 end SPL 332,408 2,218 board_init_f 482,688 150,280 board_init_r 808,694 326,006 id=64 845,029 36,335 id=65 845,730 701 main_loop 3,281,876 2,436,146 id=175 Accumulated time: 3,169 dm_spl 36,041 dm_f 41,701 dm_r STM32MP> bootstage report Timer summary in microseconds (12 records): Mark Elapsed Stage 0 0 reset 211,036 211,036 SPL 343,393 132,357 end SPL 345,645 2,252 board_init_f 496,596 150,951 board_init_r 822,256 325,660 id=64 858,451 36,195 id=65 859,153 702 main_loop 3,414,706 2,555,553 id=175 Accumulated time: 3,132 dm_spl 36,005 dm_f 41,695 dm_r Changes in v4: - fix commit message and comment and add Patrice Chotard reviewed-by - fix commit message and add Patrice Chotard reviewed-by Changes in v3: - add Information in commit-message on early malloc and .BSS - remove debug message "bye" Changes in v2: - create a new function early_enable_caches - use TLB in .init section - use the default weak dram_bank_mmu_setup() and use mmu_set_region_dcache_behaviour() to setup the early MMU configuration - enable data cache on DDR in SPL, after DDR controller initialization - new Patrick Delaunay (2): arm: stm32mp: activate data cache in SPL and before relocation arm: stm32mp: activate data cache on DDR in SPL arch/arm/mach-stm32mp/cpu.c | 43 ++++++++++++++++++++++++++++++++++++- arch/arm/mach-stm32mp/spl.c | 19 ++++++++++++++++ 2 files changed, 61 insertions(+), 1 deletion(-) -- 2.17.1
