On Thu, Apr 30, 2020 at 7:47 AM Frank Wang <frank.w...@rock-chips.com> wrote: > > This implements the Type-C PHY driver for Rockchip platform > with Cadence IP block. > > Signed-off-by: Frank Wang <frank.w...@rock-chips.com> > Signed-off-by: William Wu <william...@rock-chips.com> > --- > drivers/phy/Kconfig | 7 + > drivers/phy/Makefile | 1 + > drivers/phy/phy-rockchip-typec.c | 523 +++++++++++++++++++++++++ > include/linux/usb/rockchip_phy_typec.h | 52 +++ > 4 files changed, 583 insertions(+) > create mode 100644 drivers/phy/phy-rockchip-typec.c > create mode 100644 include/linux/usb/rockchip_phy_typec.h > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig > index a72f34f0d4..07a060a78a 100644 > --- a/drivers/phy/Kconfig > +++ b/drivers/phy/Kconfig > @@ -90,6 +90,13 @@ config PHY_DA8XX_USB > help > Enable this to support the USB PHY on DA8xx SoCs. > > +config PHY_ROCKCHIP_TYPEC > + bool "Support Rockchip TYPEC PHY Driver" > + depends on ARCH_ROCKCHIP > + select PHY > + help > + Enable this to support the Rockchip USB Type-C PHY. > + > config PIPE3_PHY > bool "Support omap's PIPE3 PHY" > depends on PHY && ARCH_OMAP2PLUS > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile > index 43ce62e08c..9ed721b1d5 100644 > --- a/drivers/phy/Makefile > +++ b/drivers/phy/Makefile > @@ -15,6 +15,7 @@ obj-$(CONFIG_AM654_PHY) += phy-ti-am654.o > obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o > obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o > obj-$(CONFIG_PHY_RCAR_GEN3) += phy-rcar-gen3.o > +obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o > obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o > obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o > obj-$(CONFIG_MESON_G12A_USB_PHY) += meson-g12a-usb2.o meson-g12a-usb3-pcie.o > diff --git a/drivers/phy/phy-rockchip-typec.c > b/drivers/phy/phy-rockchip-typec.c > new file mode 100644 > index 0000000000..2e8c8c8ffe > --- /dev/null > +++ b/drivers/phy/phy-rockchip-typec.c > @@ -0,0 +1,523 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2020 Rockchip Electronics Co., Ltd > + * > + * Based on drivers/phy/rockchip/phy-rockchip-typec.c in Linux Kernel. > + */ > + > +#include <common.h> > +#include <dm.h> > +#include <dm/device_compat.h> > +#include <dm/lists.h> > +#include <dm/of_access.h> > +#include <generic-phy.h> > +#include <power/regulator.h> > +#include <regmap.h> > +#include <reset.h> > +#include <syscon.h> > +#include <asm-generic/io.h> > +#include <asm/arch/clock.h>
drivers/phy/phy-rockchip-typec.c:19:28: fatal error: asm/arch/clock.h: No such file or directory #include <asm/arch/clock.h> > +#include <linux/iopoll.h> > +#include <linux/usb/rockchip_phy_typec.h> > + > +#define CMN_PLL0_VCOCAL_OVRD (0x83 << 2) > +#define CMN_PLL0_VCOCAL_INIT (0x84 << 2) > +#define CMN_PLL0_VCOCAL_ITER (0x85 << 2) > +#define CMN_PLL0_LOCK_REFCNT_START (0x90 << 2) > +#define CMN_PLL0_LOCK_PLLCNT_START (0x92 << 2) > +#define CMN_PLL0_LOCK_PLLCNT_THR (0x93 << 2) > +#define CMN_PLL0_INTDIV (0x94 << 2) > +#define CMN_PLL0_FRACDIV (0x95 << 2) > +#define CMN_PLL0_HIGH_THR (0x96 << 2) > +#define CMN_PLL0_DSM_DIAG (0x97 << 2) > +#define CMN_PLL0_SS_CTRL1 (0x98 << 2) > +#define CMN_PLL0_SS_CTRL2 (0x99 << 2) > +#define CMN_DIAG_PLL0_FBH_OVRD (0x1c0 << 2) > +#define CMN_DIAG_PLL0_FBL_OVRD (0x1c1 << 2) > +#define CMN_DIAG_PLL0_OVRD (0x1c2 << 2) > +#define CMN_DIAG_PLL0_V2I_TUNE (0x1c5 << 2) > +#define CMN_DIAG_PLL0_CP_TUNE (0x1c6 << 2) > +#define CMN_DIAG_PLL0_LF_PROG (0x1c7 << 2) > +#define CMN_DIAG_HSCLK_SEL (0x1e0 << 2) > + > +#define TX_TXCC_MGNFS_MULT_000(n) ((0x4050 | ((n) << 9)) << 2) > +#define XCVR_DIAG_PLLDRC_CTRL(n) ((0x40e0 | ((n) << 9)) << 2) > +#define XCVR_DIAG_BIDI_CTRL(n) ((0x40e8 | ((n) << 9)) << 2) > +#define XCVR_DIAG_LANE_FCM_EN_MGN(n) ((0x40f2 | ((n) << 9)) << 2) > +#define TX_PSC_A0(n) ((0x4100 | ((n) << 9)) << 2) > +#define TX_PSC_A1(n) ((0x4101 | ((n) << 9)) << 2) > +#define TX_PSC_A2(n) ((0x4102 | ((n) << 9)) << 2) > +#define TX_PSC_A3(n) ((0x4103 | ((n) << 9)) << 2) > +#define TX_RCVDET_CTRL(n) ((0x4120 | ((n) << 9)) << 2) > +#define TX_RCVDET_EN_TMR(n) ((0x4122 | ((n) << 9)) << 2) > +#define TX_RCVDET_ST_TMR(n) ((0x4123 | ((n) << 9)) << 2) > +#define TX_DIAG_TX_DRV(n) ((0x41e1 | ((n) << 9)) << 2) > +#define TX_DIAG_BGREF_PREDRV_DELAY (0x41e7 << 2) > + > +#define RX_PSC_A0(n) ((0x8000 | ((n) << 9)) << 2) > +#define RX_PSC_A1(n) ((0x8001 | ((n) << 9)) << 2) > +#define RX_PSC_A2(n) ((0x8002 | ((n) << 9)) << 2) > +#define RX_PSC_A3(n) ((0x8003 | ((n) << 9)) << 2) > +#define RX_PSC_CAL(n) ((0x8006 | ((n) << 9)) << 2) > +#define RX_PSC_RDY(n) ((0x8007 | ((n) << 9)) << 2) > +#define RX_SIGDET_HL_FILT_TMR(n) ((0x8090 | ((n) << 9)) << 2) > +#define RX_REE_CTRL_DATA_MASK(n) ((0x81bb | ((n) << 9)) << 2) > +#define RX_DIAG_SIGDET_TUNE(n) ((0x81dc | ((n) << 9)) << 2) > +#define RX_DIAG_SC2C_DELAY (0x81e1 << 2) > + > +#define PHY_ISO_CMN_CTRL (0xc010 << 2) > +#define PMA_CMN_CTRL1 (0xc800 << 2) > +#define PHY_PMA_ISO_CMN_CTRL (0xc810 << 2) > +#define PHY_ISOLATION_CTRL (0xc81f << 2) > +#define PHY_PMA_ISO_XCVR_CTRL(n) ((0xcc11 | ((n) << 6)) << 2) > +#define PHY_PMA_ISO_LINK_MODE(n) ((0xcc12 | ((n) << 6)) << 2) > +#define PHY_PMA_ISO_PWRST_CTRL(n) ((0xcc13 | ((n) << 6)) << 2) > +#define PHY_PMA_ISO_TX_DATA_LO(n) ((0xcc14 | ((n) << 6)) << 2) > +#define PHY_PMA_ISO_TX_DATA_HI(n) ((0xcc15 | ((n) << 6)) << 2) > +#define PHY_PMA_ISO_RX_DATA_LO(n) ((0xcc16 | ((n) << 6)) << 2) > +#define PHY_PMA_ISO_RX_DATA_HI(n) ((0xcc17 | ((n) << 6)) << 2) > + > +/* > + * Selects which PLL clock will be driven on the analog high speed > + * clock 0: PLL 0 div 1 > + * clock 1: PLL 1 div 2 > + */ > +#define CLK_PLL1_DIV1 0x20 > +#define CLK_PLL1_DIV2 0x30 > +#define CLK_PLL_MASK 0x33 > + > +#define CMN_READY BIT(0) > +#define PHY_MODE_SET_TIMEOUT 100000 > +#define MODE_DISCONNECT 0 > +#define MODE_UFP_USB BIT(0) > +#define MODE_DFP_USB BIT(1) > +#define POWER_ON_TRIES 5 > + > +struct phy_reg { > + u16 value; > + u32 addr; > +}; > + > +static const struct phy_reg usb3_pll_cfg[] = { > + { 0xf0, CMN_PLL0_VCOCAL_INIT }, > + { 0x18, CMN_PLL0_VCOCAL_ITER }, > + { 0xd0, CMN_PLL0_INTDIV }, > + { 0x4a4a, CMN_PLL0_FRACDIV }, > + { 0x34, CMN_PLL0_HIGH_THR }, > + { 0x1ee, CMN_PLL0_SS_CTRL1 }, > + { 0x7f03, CMN_PLL0_SS_CTRL2 }, > + { 0x20, CMN_PLL0_DSM_DIAG }, > + { 0, CMN_DIAG_PLL0_OVRD }, > + { 0, CMN_DIAG_PLL0_FBH_OVRD }, > + { 0, CMN_DIAG_PLL0_FBL_OVRD }, > + { 0x7, CMN_DIAG_PLL0_V2I_TUNE }, > + { 0x45, CMN_DIAG_PLL0_CP_TUNE }, > + { 0x8, CMN_DIAG_PLL0_LF_PROG }, > +}; > + > +static void tcphy_cfg_24m(struct rockchip_typec_phy *tcphy) > +{ > + u32 i, rdata; > + > + /* > + * cmn_ref_clk_sel = 3, select the 24Mhz for clk parent > + * cmn_psm_clk_dig_div = 2, set the clk division to 2 > + */ > + writel(0x830, tcphy->base + PMA_CMN_CTRL1); > + for (i = 0; i < 4; i++) { > + /* > + * The following PHY configuration assumes a 24 MHz reference > + * clock. > + */ > + writel(0x90, tcphy->base + XCVR_DIAG_LANE_FCM_EN_MGN(i)); > + writel(0x960, tcphy->base + TX_RCVDET_EN_TMR(i)); > + writel(0x30, tcphy->base + TX_RCVDET_ST_TMR(i)); > + } > + > + rdata = readl(tcphy->base + CMN_DIAG_HSCLK_SEL); > + rdata &= ~CLK_PLL_MASK; > + rdata |= CLK_PLL1_DIV2; > + writel(rdata, tcphy->base + CMN_DIAG_HSCLK_SEL); > +} > + > +static void tcphy_cfg_usb3_pll(struct rockchip_typec_phy *tcphy) > +{ > + u32 i; > + > + /* load the configuration of PLL0 */ > + for (i = 0; i < ARRAY_SIZE(usb3_pll_cfg); i++) > + writel(usb3_pll_cfg[i].value, > + tcphy->base + usb3_pll_cfg[i].addr); > +} > + > +static void tcphy_tx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 > lane) > +{ > + writel(0x7799, tcphy->base + TX_PSC_A0(lane)); > + writel(0x7798, tcphy->base + TX_PSC_A1(lane)); > + writel(0x5098, tcphy->base + TX_PSC_A2(lane)); > + writel(0x5098, tcphy->base + TX_PSC_A3(lane)); > + writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane)); > + writel(0xbf, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane)); > +} > + > +static void tcphy_rx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 > lane) > +{ > + writel(0xa6fd, tcphy->base + RX_PSC_A0(lane)); > + writel(0xa6fd, tcphy->base + RX_PSC_A1(lane)); > + writel(0xa410, tcphy->base + RX_PSC_A2(lane)); > + writel(0x2410, tcphy->base + RX_PSC_A3(lane)); > + writel(0x23ff, tcphy->base + RX_PSC_CAL(lane)); > + writel(0x13, tcphy->base + RX_SIGDET_HL_FILT_TMR(lane)); > + writel(0x03e7, tcphy->base + RX_REE_CTRL_DATA_MASK(lane)); > + writel(0x1004, tcphy->base + RX_DIAG_SIGDET_TUNE(lane)); > + writel(0x2010, tcphy->base + RX_PSC_RDY(lane)); > + writel(0xfb, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane)); > +} > + > +static inline int property_enable(struct rockchip_typec_phy *tcphy, > + const struct usb3phy_reg *reg, bool en) > +{ > + u32 mask = 1 << reg->write_enable; > + u32 val = en << reg->enable_bit; > + > + return writel((val | mask), (tcphy->grf_regs + reg->offset)); > +} > + > +static int tcphy_cfg_usb3_to_usb2_only(struct rockchip_typec_phy *tcphy, > + bool value) > +{ > + struct rockchip_usb3phy_port_cfg *cfg = &tcphy->port_cfgs; > + > + property_enable(tcphy, &cfg->usb3tousb2_en, value); > + property_enable(tcphy, &cfg->usb3host_disable, value); > + property_enable(tcphy, &cfg->usb3host_port, !value); > + > + return 0; > +} > + > +static int tcphy_phy_init(struct rockchip_typec_phy *tcphy) > +{ > + struct rockchip_usb3phy_port_cfg *cfg = &tcphy->port_cfgs; > + int ret; > + u32 val; > + > + reset_deassert(&tcphy->tcphy_rst); > + > + property_enable(tcphy, &cfg->typec_conn_dir, tcphy->flip); > + > + tcphy_cfg_24m(tcphy); > + > + tcphy_cfg_usb3_pll(tcphy); > + if (tcphy->flip) { > + tcphy_tx_usb3_cfg_lane(tcphy, 3); > + tcphy_rx_usb3_cfg_lane(tcphy, 2); > + } else { > + tcphy_tx_usb3_cfg_lane(tcphy, 0); > + tcphy_rx_usb3_cfg_lane(tcphy, 1); > + } > + > + reset_deassert(&tcphy->uphy_rst); > + > + ret = readx_poll_timeout(readl, tcphy->base + PMA_CMN_CTRL1, > + val, val & CMN_READY, PHY_MODE_SET_TIMEOUT); Please use readl_poll_timeout, now the poll_timeout API has sleep_us so readx would mostly have another argument of sleep_us. Jagan.