On Sat, May 2, 2020 at 10:05 PM Pragnesh Patel <pragnesh.pa...@sifive.com> wrote: > > Hi Jagan, > > >-----Original Message----- > >From: Jagan Teki <ja...@amarulasolutions.com> > >Sent: 02 May 2020 21:44 > >To: Pragnesh Patel <pragnesh.pa...@sifive.com> > >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra > ><atish.pa...@wdc.com>; Palmer Dabbelt <palmerdabb...@google.com>; Bin > >Meng <bmeng...@gmail.com>; Paul Walmsley <paul.walms...@sifive.com>; > >Troy Benjegerdes <troy.benjeger...@sifive.com>; Anup Patel > ><anup.pa...@wdc.com>; Sagar Kadam <sagar.ka...@sifive.com>; Rick Chen > ><r...@andestech.com>; Lukasz Majewski <lu...@denx.de>; Anatolij > >Gustschin <ag...@denx.de>; Simon Glass <s...@chromium.org> > >Subject: Re: [PATCH v7 10/22] clk: sifive: fu540-prci: ddr and ethernet clock > >initialization in SPL > > > >[External Email] Do not click links or attachments unless you recognize the > >sender and know the content is safe > > > >On Sat, May 2, 2020 at 3:38 PM Pragnesh Patel <pragnesh.pa...@sifive.com> > >wrote: > >> > >> Add ddr clock release reset and ehternet clock initialization for SPL > > > >Why ethernet still require for SPL? > > I think we have already discussed this in v6. > https://patchwork.ozlabs.org/project/uboot/patch/20200329170538.25449-10-pragnesh.pa...@sifive.com/
Understand, then make a separate patch for "Ethernet SPL" but not in this series.
