On 5/2/20 5:03 PM, Daniel Schwierzeck wrote:
>
>
> Am 02.05.20 um 17:00 schrieb Daniel Schwierzeck:
>> Hi Marek,
>>
>> Am 18.04.20 um 05:15 schrieb Marek Vasut:
>>> Replace the PCI IO access with PCI memory access, the card
>>> supports both, but the former does not work with QEMU SH4.
>>>
>>> Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
>>> Cc: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
>>> Cc: Joe Hershberger <joe.hershber...@ni.com>
>>> ---
>>> Note: It would be good to test this on the mips malta
>>> ---
>>> drivers/net/pcnet.c | 6 +++---
>>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>>
> ...
>>
>>
>> Contrary to SH there is a difference between memory access and IO access
>> on MIPS. So you have to replace also all inw()/outw() with
>> readw()/writew() like so:
>>
>> static u16 pcnet_read_csr(struct eth_device *dev, int index)
>> {
>> - writew(index, dev->iobase + PCNET_RAP);
>> - return readw(dev->iobase + PCNET_RDP);
>> + void __iomem *base = (void __iomem *)dev->iobase;
>> + writew(index, base + PCNET_RAP);
>> + return readw(base + PCNET_RDP);
>> }
>
> sorry wrong diff, I meant:
>
> static u16 pcnet_read_csr(struct eth_device *dev, int index)
> {
> - outw(index, dev->iobase + PCNET_RAP);
> - return inw(dev->iobase + PCNET_RDP);
> + void __iomem *base = (void __iomem *)dev->iobase;
> + writew(index, base + PCNET_RAP);
> + return readw(base + PCNET_RDP);
> }
I'm CCing Tom. He didn't pick the PR yet.
If you want to send it as separate patch, fine by me, maybe Tom can pick
that one right after the PR ; or I can squash it into the PR. I think
the former would be easier.
--
Best regards,
Marek Vasut
