Some PCI Express register offsets are currently defined in multiple
drivers, move them to a common header to avoid re-definitions and
as a pre-requisite for adding new PCIe driver.
While at it replace some spaces with tabs.
Signed-off-by: Sylwester Nawrocki <s.nawro...@samsung.com>
Reviewed-by: Bin Meng <bmeng...@gmail.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulie...@suse.de>
---
Changes since v1:
- none.
Changes since RFC:
- whitespace clean up.
---
drivers/pci/pci-rcar-gen3.c | 8 --------
drivers/pci/pcie_intel_fpga.c | 3 ---
include/pci.h | 13 +++++++++++--
3 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
index 30eff67..393f1c9 100644
--- a/drivers/pci/pci-rcar-gen3.c
+++ b/drivers/pci/pci-rcar-gen3.c
@@ -117,14 +117,6 @@
#define RCAR_PCI_MAX_RESOURCES 4
#define MAX_NR_INBOUND_MAPS 6
-#define PCI_EXP_FLAGS 2 /* Capabilities register */
-#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
-#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
-#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
-#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active
Reporting Capable */
-#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
-#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
-
enum {
RCAR_PCI_ACCESS_READ,
RCAR_PCI_ACCESS_WRITE,
diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
index 6a9f29c..69363a0 100644
--- a/drivers/pci/pcie_intel_fpga.c
+++ b/drivers/pci/pcie_intel_fpga.c
@@ -65,9 +65,6 @@
#define IS_ROOT_PORT(pcie, bdf) \
((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
-#define PCI_EXP_LNKSTA 18 /* Link Status */
-#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
-
/**
* struct intel_fpga_pcie - Intel FPGA PCIe controller state
* @bus: Pointer to the PCI bus
diff --git a/include/pci.h b/include/pci.h
index aff56b2..dfdbb32 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -471,10 +471,19 @@
#define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */
/* PCI Express capabilities */
+#define PCI_EXP_FLAGS 2 /* Capabilities register */
+#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
+#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
#define PCI_EXP_DEVCAP 4 /* Device capabilities */
-#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
+#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
#define PCI_EXP_DEVCTL 8 /* Device Control */
-#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
+#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry /
FLR */
+#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
+#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link
Active Reporting Capable */
+#define PCI_EXP_LNKSTA 18 /* Link Status */
+#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
+#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
+#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
/* Include the ID list */
--
2.7.4
