On Fri, May 22, 2020 at 6:18 AM Alex Nemirovsky <alex.nemirov...@cortina-access.com> wrote: > > From: Pengpeng Chen <pengpeng.c...@cortina-access.com> > > Add SPI Flash controller driver for Cortina Access > CAxxxx SoCs > > Signed-off-by: Pengpeng Chen <pengpeng.c...@cortina-access.com> > Signed-off-by: Alex Nemirovsky <alex.nemirov...@cortina-access.com> > CC: Jagan Teki <ja...@amarulasolutions.com> > CC: Vignesh R <vigne...@ti.com> > CC: Tom Rini <tr...@konsulko.com> > > --- > > Changes in v8: > - No code change > - Split out individual driver from Cortina Package 2 patch series > to help streamline acceptence into master > > Changes in v7: > - Replace substring "OPCODE" with "OP" in MACROs to help > reduce code line lengths > - Replace substring "_MASK" with "_MSK" in MACROs to help > reduce code line lengths > > Changes in v5: None > Changes in v3: > - Fixup syntax issues related to checkpatch.pl cleanup > > MAINTAINERS | 8 + > drivers/spi/Kconfig | 8 + > drivers/spi/Makefile | 1 + > drivers/spi/ca_sflash.c | 576 > ++++++++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 593 insertions(+) > create mode 100644 drivers/spi/ca_sflash.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 8add9d4..57ce45e 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -181,6 +181,10 @@ F: drivers/gpio/cortina_gpio.c > F: drivers/watchdog/cortina_wdt.c > F: drivers/serial/serial_cortina.c > F: drivers/mmc/ca_dw_mmc.c > +F: drivers/i2c/i2c-cortina.c > +F: drivers/i2c/i2c-cortina.h > +F: drivers/led/led_cortina.c > +F: drivers/spi/ca_sflash.c > > ARM/CZ.NIC TURRIS MOX SUPPORT > M: Marek Behun <marek.be...@nic.cz> > @@ -732,6 +736,10 @@ F: drivers/gpio/cortina_gpio.c > F: drivers/watchdog/cortina_wdt.c > F: drivers/serial/serial_cortina.c > F: drivers/mmc/ca_dw_mmc.c > +F: drivers/i2c/i2c-cortina.c > +F: drivers/i2c/i2c-cortina.h > +F: drivers/led/led_cortina.c
These changes are unrelated to SPI, keep out of this patch. > +F: drivers/spi/ca_sflash.c > > MIPS MSCC > M: Gregory CLEMENT <gregory.clem...@bootlin.com> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index dccd5ea..09f2a2a 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -106,6 +106,14 @@ config BCMSTB_SPI > be used to access the SPI flash on platforms embedding this > Broadcom SPI core. > > +config CORTINA_SFLASH > + bool "Cortina-Access Serial Flash controller driver" > + depends on DM_SPI && SPI_MEM > + help > + Enable the Cortina-Access Serial Flash controller driver. This > driver > + can be used to access the SPI NOR/NAND flash on platforms embedding > this > + Cortina-Access IP core. > + > config CADENCE_QSPI > bool "Cadence QSPI driver" > help > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index 6441694..5e53f11 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -25,6 +25,7 @@ obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o > obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o > obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o > obj-$(CONFIG_CF_SPI) += cf_spi.o > +obj-$(CONFIG_CORTINA_SFLASH) += ca_sflash.o > obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o > obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o > obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o > diff --git a/drivers/spi/ca_sflash.c b/drivers/spi/ca_sflash.c > new file mode 100644 > index 0000000..00af6bf > --- /dev/null > +++ b/drivers/spi/ca_sflash.c > @@ -0,0 +1,576 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Driver for Cortina SPI-FLASH Controller > + * > + * Copyright (C) 2020 Cortina Access Inc. All Rights Reserved. > + * > + * Author: PengPeng Chen <pengpeng.c...@cortina-access.com> > + */ > + > +#include <common.h> > +#include <malloc.h> > +#include <clk.h> > +#include <dm.h> > +#include <errno.h> > +#include <fdtdec.h> > +#include <linux/compat.h> > +#include <linux/io.h> > +#include <linux/iopoll.h> > +#include <linux/ioport.h> > +#include <linux/sizes.h> > +#include <spi.h> > +#include <spi-mem.h> > +#include <reset.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +struct ca_sflash_regs { > + u32 idr; /* 0x00:Flash word ID Register */ > + u32 tc; /* 0x04:Flash Timeout Counter Register */ > + u32 sr; /* 0x08:Flash Status Register */ > + u32 tr; /* 0x0C:Flash Type Register */ > + u32 asr; /* 0x10:Flash ACCESS START/BUSY Register */ > + u32 isr; /* 0x14:Flash Interrupt Status Register */ > + u32 imr; /* 0x18:Flash Interrupt Mask Register */ > + u32 fcr; /* 0x1C:NAND Flash FIFO Control Register */ > + u32 ffsr; /* 0x20:Flash FIFO Status Register */ > + u32 ffar; /* 0x24:Flash FIFO ADDRESS Register */ > + u32 ffmar; /* 0x28:Flash FIFO MATCHING ADDRESS Register > */ > + u32 ffdr; /* 0x2C:Flash FIFO Data Register */ > + u32 ar; /* 0x30:Serial Flash Access Register */ > + u32 ear; /* 0x34:Serial Flash Extend Access Register */ > + u32 adr; /* 0x38:Serial Flash ADdress Register */ > + u32 dr; /* 0x3C:Serial Flash Data Register */ > + u32 tmr; /* 0x40:Serial Flash Timing Register */ > +}; > + > +/* > + * FLASH_TYPE > + */ > +#define CA_FLASH_TR_PIN BIT(15) > +#define CA_FLASH_TR_TYPE_MSK GENMASK(14, 12) > +#define CA_FLASH_TR_TYPE(tp) (((tp) << 12) & CA_FLASH_TR_TYPE_MSK) > +#define CA_FLASH_TR_WIDTH BIT(11) > +#define CA_FLASH_TR_SIZE_MSK GENMASK(10, 9) > +#define CA_FLASH_TR_SIZE(sz) (((sz) << 9) & CA_FLASH_TR_SIZE_MSK) > + > +/* > + * FLASH_FLASH_ACCESS_START > + */ > +#define CA_FLASH_ASR_IND_START_EN BIT(1) > +#define CA_FLASH_ASR_DMA_START_EN BIT(3) > +#define CA_FLASH_ASR_WR_ACCESS_EN BIT(9) > + > +/* > + * FLASH_FLASH_INTERRUPT > + */ > +#define CA_FLASH_ISR_REG_IRQ BIT(1) > +#define CA_FLASH_ISR_FIFO_IRQ BIT(2) > + > +/* > + * FLASH_SF_ACCESS > + */ > +#define CA_SF_AR_OP_MSK GENMASK(7, 0) > +#define CA_SF_AR_OP(op) ((op) << 0 & CA_SF_AR_OP_MSK) > +#define CA_SF_AR_ACCODE_MSK GENMASK(11, 8) > +#define CA_SF_AR_ACCODE(ac) (((ac) << 8) & CA_SF_AR_ACCODE_MSK) > +#define CA_SF_AR_FORCE_TERM BIT(12) > +#define CA_SF_AR_FORCE_BURST BIT(13) > +#define CA_SF_AR_AUTO_MODE_EN BIT(15) > +#define CA_SF_AR_CHIP_EN_ALT BIT(16) > +#define CA_SF_AR_HI_SPEED_RD BIT(17) > +#define CA_SF_AR_MIO_INF_DC BIT(24) > +#define CA_SF_AR_MIO_INF_AC BIT(25) > +#define CA_SF_AR_MIO_INF_CC BIT(26) > +#define CA_SF_AR_DDR_MSK GENMASK(29, 28) > +#define CA_SF_AR_DDR(ddr) (((ddr) << 28) & CA_SF_AR_DDR_MSK) > +#define CA_SF_AR_MIO_INF_MSK GENMASK(31, 30) > +#define CA_SF_AR_MIO_INF(io) (((io) << 30) & CA_SF_AR_MIO_INF_MSK) > + > +/* > + * FLASH_SF_EXT_ACCESS > + */ > +#define CA_SF_EAR_OP_MSK GENMASK(7, 0) > +#define CA_SF_EAR_OP(op) (((op) << 0) & CA_SF_EAR_OP_MSK) > +#define CA_SF_EAR_DATA_CNT_MSK GENMASK(20, 8) > +#define CA_SF_EAR_DATA_CNT(cnt) (((cnt) << 8) & > CA_SF_EAR_DATA_CNT_MSK) > +#define CA_SF_EAR_DATA_CNT_MAX (4096) > +#define CA_SF_EAR_ADDR_CNT_MSK GENMASK(23, 21) > +#define CA_SF_EAR_ADDR_CNT(cnt) (((cnt) << 21) & > CA_SF_EAR_ADDR_CNT_MSK) > +#define CA_SF_EAR_ADDR_CNT_MAX (5) > +#define CA_SF_EAR_DUMY_CNT_MSK GENMASK(29, 24) > +#define CA_SF_EAR_DUMY_CNT(cnt) (((cnt) << 24) & > CA_SF_EAR_DUMY_CNT_MSK) > +#define CA_SF_EAR_DUMY_CNT_MAX (32) > +#define CA_SF_EAR_DRD_CMD_EN BIT(31) > + > +/* > + * FLASH_SF_ADDRESS > + */ > +#define CA_SF_ADR_REG_MSK GENMASK(31, 0) > +#define CA_SF_ADR_REG(addr) (((addr) << 0) & CA_SF_ADR_REG_MSK) > + > +/* > + * FLASH_SF_DATA > + */ > +#define CA_SF_DR_REG_MSK GENMASK(31, 0) > +#define CA_SF_DR_REG(addr) (((addr) << 0) & CA_SF_DR_REG_MSK) > + > +/* > + * FLASH_SF_TIMING > + */ > +#define CA_SF_TMR_IDLE_MSK GENMASK(7, 0) > +#define CA_SF_TMR_IDLE(idle) (((idle) << 0) & CA_SF_TMR_IDLE_MSK) > +#define CA_SF_TMR_HOLD_MSK GENMASK(15, 8) > +#define CA_SF_TMR_HOLD(hold) (((hold) << 8) & CA_SF_TMR_HOLD_MSK) > +#define CA_SF_TMR_SETUP_MSK GENMASK(23, 16) > +#define CA_SF_TMR_SETUP(setup) (((setup) << 16) & > CA_SF_TMR_SETUP_MSK) > +#define CA_SF_TMR_CLK_MSK GENMASK(26, 24) > +#define CA_SF_TMR_CLK(clk) (((clk) << 24) & CA_SF_TMR_CLK_MSK) > + > +#define CA_SFLASH_IND_WRITE 0 > +#define CA_SFLASH_IND_READ 1 > +#define CA_SFLASH_MEM_MAP 3 > +#define CA_SFLASH_FIFO_TIMEOUT_US 30000 > +#define CA_SFLASH_BUSY_TIMEOUT_US 40000 > + > +#define CA_SF_AC_OP 0x00 > +#define CA_SF_AC_OP_1_DATA 0x01 > +#define CA_SF_AC_OP_2_DATA 0x02 > +#define CA_SF_AC_OP_3_DATA 0x03 > +#define CA_SF_AC_OP_4_DATA 0x04 > +#define CA_SF_AC_OP_3_ADDR 0x05 > +#define CA_SF_AC_OP_4_ADDR (CA_SF_AC_OP_3_ADDR) > +#define CA_SF_AC_OP_3_ADDR_1_DATA 0x06 > +#define CA_SF_AC_OP_4_ADDR_1_DATA (CA_SF_AC_OP_3_ADDR_1_DATA << 2) > +#define CA_SF_AC_OP_3_ADDR_2_DATA 0x07 > +#define CA_SF_AC_OP_4_ADDR_2_DATA (CA_SF_AC_OP_3_ADDR_2_DATA << 2) > +#define CA_SF_AC_OP_3_ADDR_3_DATA 0x08 > +#define CA_SF_AC_OP_4_ADDR_3_DATA (CA_SF_AC_OP_3_ADDR_3_DATA << 2) > +#define CA_SF_AC_OP_3_ADDR_4_DATA 0x09 > +#define CA_SF_AC_OP_4_ADDR_4_DATA (CA_SF_AC_OP_3_ADDR_4_DATA << 2) > +#define CA_SF_AC_OP_3_ADDR_X_1_DATA 0x0A > +#define CA_SF_AC_OP_4_ADDR_X_1_DATA (CA_SF_AC_OP_3_ADDR_X_1_DATA << 2) > +#define CA_SF_AC_OP_3_ADDR_X_2_DATA 0x0B > +#define CA_SF_AC_OP_4_ADDR_X_2_DATA (CA_SF_AC_OP_3_ADDR_X_2_DATA << 2) > +#define CA_SF_AC_OP_3_ADDR_X_3_DATA 0x0C > +#define CA_SF_AC_OP_4_ADDR_X_3_DATA (CA_SF_AC_OP_3_ADDR_X_3_DATA << 2) > +#define CA_SF_AC_OP_3_ADDR_X_4_DATA 0x0D > +#define CA_SF_AC_OP_4_ADDR_X_4_DATA (CA_SF_AC_OP_3_ADDR_X_4_DATA << 2) > +#define CA_SF_AC_OP_3_ADDR_4X_1_DATA 0x0E > +#define CA_SF_AC_OP_4_ADDR_4X_1_DATA (CA_SF_AC_OP_3_ADDR_4X_1_DATA << 2) > +#define CA_SF_AC_OP_EXTEND 0x0F > + > +#define CA_SF_ACCESS_MIO_SINGLE 0 > +#define CA_SF_ACCESS_MIO_DUAL 1 > +#define CA_SF_ACCESS_MIO_QUARD 2 Seems like all opcode functionalities are the similar way how flash behaves, why can't we right a flash controller driver mtd side? Do you have Linux driver for this?