Hi Sagar, On Fri, Jun 26, 2020 at 1:14 AM Sagar Kadam <sagar.ka...@sifive.com> wrote: > > Hello Bin, > > > -----Original Message----- > > From: Bin Meng <bmeng...@gmail.com> > > Sent: Tuesday, June 23, 2020 11:00 AM > > To: Rick Chen <r...@andestech.com>; Simon Glass <s...@chromium.org>; > > Pragnesh Patel <pragnesh.pa...@sifive.com>; Sagar Kadam > > <sagar.ka...@sifive.com>; U-Boot Mailing List <u-boot@lists.denx.de> > > Cc: Bin Meng <bin.m...@windriver.com> > > Subject: [PATCH 3/5] riscv: Do not build reset.c if SYSRESET is on > > > > [External Email] Do not click links or attachments unless you recognize the > > sender and know the content is safe > > > > From: Bin Meng <bin.m...@windriver.com> > > > > SYSRESET uclass driver already provides all the reset APIs, hence > > exclude our own ad-hoc reset.c implementation. > > > > Signed-off-by: Bin Meng <bin.m...@windriver.com> > > --- > > > > arch/riscv/lib/Makefile | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile > > index b5e9324..6c503ff 100644 > > --- a/arch/riscv/lib/Makefile > > +++ b/arch/riscv/lib/Makefile > > @@ -20,7 +20,9 @@ obj-$(CONFIG_SBI) += sbi.o > > obj-$(CONFIG_SBI_IPI) += sbi_ipi.o > > endif > > obj-y += interrupts.o > > +ifeq ($(CONFIG_$(SPL_)SYSRESET),) > > obj-y += reset.o > > +endif > > I could see reset get's built when SYSRESET in enabled > CC spl/arch/riscv/lib/interrupts.o > CC spl/arch/riscv/lib/reset.o > AS spl/arch/riscv/lib/setjmp.o >
This is because we don't enable CONFIG_SPL_SYSRESET in the board config. For SPL, normally we don't need to reset. > Should this have been? > ifneq ($(CONFIG_$(SPL_)SYSRESET),) > Regards, Bin