On Mon, Jul 6, 2020 at 6:12 AM Andre Przywara <andre.przyw...@arm.com> wrote: > > When sending a command via the MDIO bus, the Designware MAC expects some > bits in the CMD register to describe the clock divider value between > the main clock and the MDIO clock. > So far we were omitting these bits, resulting in setting "00", which > means "/ 16", so ending up with an MDIO frequency of either 18.75 or > 12.5 MHz. > All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek > PHYs seem to be fine with that - although it looks like to be severly > overclocked (the MDIO spec limits the frequency to 2.5 MHz). > However the external 100Mbit PHY on the Pine64 (non-plus) board is > not happy with that, Ethernet was actually never working there, as the > PHY didn't probe.
How come the existing divider cannot work with 100Mbit external PHY(assuming external regulator pin as properly enabled) since it works with 1Gbit already? Jagan.
