[PATCH 10/12] pci: layerscape: Add size check for config resource

[Wasim Khan]

resource "config" is required to have minimum 8KB space.

Signed-off-by: Wasim Khan <wasim.k...@nxp.com>
---
 drivers/pci/pcie_layerscape.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 2f17176..8f64e53 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -493,6 +493,13 @@ static int ls_pcie_probe(struct udevice *dev)
                return ret;
        }
 
+       cfg_size = fdt_resource_size(&pcie->cfg_res);
+       if (cfg_size < SZ_8K) {
+               printf("PCIe%d: %s Invalid size(0x%x) for resource \"config\",
+                      expected minimum 0x%x \n", PCIE_SRDS_PRTCL(pcie->idx),
+                      dev->name, cfg_size, SZ_8K);
+               return 0;
+       }
        /*
         * Fix the pcie memory map address and PF control registers address
         * for LS2088A series SoCs
@@ -502,7 +509,6 @@ static int ls_pcie_probe(struct udevice *dev)
        if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
            svr == SVR_LS2048A || svr == SVR_LS2044A ||
            svr == SVR_LS2081A || svr == SVR_LS2041A) {
-               cfg_size = fdt_resource_size(&pcie->cfg_res);
                pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
                                        LS2088A_PCIE_PHYS_SIZE * pcie->idx;
                pcie->cfg_res.end = pcie->cfg_res.start + cfg_size;
-- 
2.7.4