Hi Jaehoon, Below is the full log of the performance and function tests for eMMC HS400 mode. Since I used date to record time, there must be some error more or less. I tested the r/w performance with 4G data size at 175MHz bus speed. The results were, Read: 273MB/s = 4096MB / 15s Write: 74MB/s = 4096MB / 55s
According to the eMMC data sheet the HS400 max performance for sequential r/w are, Read: 270MB/s Write: 90MB/s The performance seems to be matched and good. BTW, the test was applied two more patches to fix stability issue. Let me send out v2 patch-set with them. Thanks. ============ log ====================== NOTICE: BL2: v1.5(release):LSDK-20.04 NOTICE: BL2: Built : 05:20:45, Apr 9 2020 NOTICE: UDIMM 18ADF2G72AZ-3G2E1 NOTICE: DDR4 UDIMM with 2-rank 64-bit bus (x8) NOTICE: 32 GB DDR4, 64-bit, CL=22, ECC on, 256B, CS0+CS1 NOTICE: BL2: Booting BL31 NOTICE: BL31: v1.5(release):LSDK-20.04 NOTICE: BL31: Built : 11:00:17, Jul 15 2020 NOTICE: Welcome to LX2160 BL31 Phase U-Boot 2020.07-00703-g1b677f8 (Jul 17 2020 - 16:30:43 +0800) SoC: LX2160ACE Rev2.0 (0x87360020) Clock Configuration: CPU0(A72):2000 MHz CPU1(A72):2000 MHz CPU2(A72):2000 MHz CPU3(A72):2000 MHz CPU4(A72):2000 MHz CPU5(A72):2000 MHz CPU6(A72):2000 MHz CPU7(A72):2000 MHz CPU8(A72):2000 MHz CPU9(A72):2000 MHz CPU10(A72):2000 MHz CPU11(A72):2000 MHz CPU12(A72):2000 MHz CPU13(A72):2000 MHz CPU14(A72):2000 MHz CPU15(A72):2000 MHz Bus: 700 MHz DDR: 2900 MT/s Reset Configuration Word (RCW): 00000000: 50777738 24500050 00000000 00000000 00000010: 00000000 0c010000 00000000 00000000 00000020: 02e001a0 00002580 00000000 00000096 00000030: 00000000 00000000 00000000 00000000 00000040: 00000000 00000000 00000000 00000000 00000050: 00000000 00000000 00000000 00000000 00000060: 00000000 00000000 00027000 00000000 00000070: 08b30010 00150020 Model: NXP Layerscape LX2160ARDB Board Board: LX2160ACE Rev2.0-RDB, Board version: B, boot from FlexSPI DEV#1 FPGA: v7.0 SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz VID: Core voltage after adjustment is at 852 mV DRAM: 31.9 GiB DDR 31.9 GiB (DDR4, 64-bit, CL=22, ECC on) DDR Controller Interleaving Mode: 256B DDR Chip-Select Interleaving Mode: CS0+CS1 Using SERDES1 Protocol: 19 (0x13) Using SERDES2 Protocol: 5 (0x5) Using SERDES3 Protocol: 2 (0x2) PCIe0: pcie@3400000 disabled PCIe1: pcie@3500000 disabled PCIe2: pcie@3600000 Root Complex: x1 gen1 PCI: Failed autoconfig bar 18 PCIe3: pcie@3700000 disabled PCIe4: pcie@3800000 Root Complex: no link PCIe5: pcie@3900000 disabled MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from SPI Flash... SF: Detected mt35xu512aba with page size 256 Bytes, erase size 128 KiB, total 64 MiB *** Warning - bad CRC, using default environment EEPROM: NXID v1 In: serial_pl01x Out: serial_pl01x Err: serial_pl01x Net: e1000: 68:05:ca:31:2c:73 Warning: e1000#0 MAC addresses don't match: Address in ROM is 68:05:ca:31:2c:73 Address in environment is 00:04:9f:05:84:57 eth0: DPMAC3@usxgmii, eth1: DPMAC4@usxgmii, eth2: DPMAC17@rgmii-id, eth3: DPMAC18@rgmii-id, eth4: e1000#0 SF: Detected mt35xu512aba with page size 256 Bytes, erase size 128 KiB, total 64 MiB device 0 offset 0x640000, size 0x80000 SF: 524288 bytes @ 0x640000 Read: OK device 0 offset 0xa00000, size 0x300000 SF: 3145728 bytes @ 0xa00000 Read: OK device 0 offset 0xe00000, size 0x100000 SF: 1048576 bytes @ 0xe00000 Read: OK crc32+ fsl-mc: Booting Management Complex ... SUCCESS fsl-mc: Management Complex booted (version: 10.20.4, boot status: 0x1) Hit any key to stop autoboot: 0 => mmc dev 1 switch to partitions #0, OK mmc1(part 0) is current device => mmcinfo Device: FSL_SDHC Manufacturer ID: 13 OEM: 14e Name: R1J59 Bus Speed: 175000000 Mode: HS400 (200MHz) Rd Block Len: 512 MMC version 5.0 High Capacity: Yes Capacity: 116.5 GiB Bus Width: 8-bit DDR Erase Group Size: 512 KiB HC WP Group Size: 32 MiB User Capacity: 116.5 GiB WRREL Boot Capacity: 8 MiB ENH RPMB Capacity: 4 MiB ENH Boot area 0 is not write protected Boot area 1 is not write protected => date;mmc read 81000000 0 200000;mmc read 81000000 0 200000;mmc read 81000000 0 200000;mmc read 81000000 0 200000;date Date: 2020-07-17 (Friday) Time: 7:46:18 MMC read: dev # 1, block # 0, count 2097152 ... 2097152 blocks read: OK MMC read: dev # 1, block # 0, count 2097152 ... 2097152 blocks read: OK MMC read: dev # 1, block # 0, count 2097152 ... 2097152 blocks read: OK MMC read: dev # 1, block # 0, count 2097152 ... 2097152 blocks read: OK Date: 2020-07-17 (Friday) Time: 7:46:33 => date;mmc write 81000000 0 200000;mmc write 81000000 0 200000;mmc write 81000000 0 200000;mmc write 81000000 0 200000;date Date: 2020-07-17 (Friday) Time: 7:47:08 MMC write: dev # 1, block # 0, count 2097152 ... 2097152 blocks written: OK MMC write: dev # 1, block # 0, count 2097152 ... 2097152 blocks written: OK MMC write: dev # 1, block # 0, count 2097152 ... 2097152 blocks written: OK MMC write: dev # 1, block # 0, count 2097152 ... 2097152 blocks written: OK Date: 2020-07-17 (Friday) Time: 7:48:03 => mw.l 81000000 55555555 1000;mw.l 82000000 aaaaaaaa 1000;mmc write 81000000 0 100;mmc read 82000000 0 100;cmp.b 81000000 82000000 100 MMC write: dev # 1, block # 0, count 256 ... 256 blocks written: OK MMC read: dev # 1, block # 0, count 256 ... 256 blocks read: OK Total of 256 byte(s) were the same => Best regards, Yangbo Lu > -----Original Message----- > From: Jaehoon Chung <jh80.ch...@samsung.com> > Sent: Friday, July 17, 2020 8:31 AM > To: Y.b. Lu <yangbo...@nxp.com>; u-boot@lists.denx.de; Peng Fan > <peng....@nxp.com>; Priyanka Jain <priyanka.j...@nxp.com> > Subject: Re: [PATCH 0/9] mmc: fsl_esdhc: support eMMC HS200/HS400 modes > > Hi Yangbo, > > On 7/16/20 11:29 AM, Yangbo Lu wrote: > > This patch-set is to support eMMC HS200 and HS400 speed modes for > > eSDHC, and enable them on LX2160ARDB board. > > Is there any result about performance? > > Best Regards, > Jaehoon Chung > > > > > CI build link > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Ftravis-ci > .org%2Fgithub%2Fyangbolu1991%2Fu-boot-test%2Fbuilds%2F708215558&a > mp;data=02%7C01%7Cyangbo.lu%40nxp.com%7Ca438d5eb0d9b4c7c660708 > d829e8bc25%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63730 > 5426855786897&sdata=h54G7iKDdtmVRyuU0mZ7aZ06To3EqDc%2BRL3 > 0SFYtaWE%3D&reserved=0 > > > > Yangbo Lu (9): > > mmc: add a reinit() API > > mmc: fsl_esdhc: add a reinit() callback > > mmc: fsl_esdhc: support tuning for eMMC HS200 > > mmc: fsl_esdhc: clean TBCTL[TB_EN] manually during init > > mmc: add a hs400_tuning flag > > mmc: add a mmc_hs400_prepare_ddr() interface > > mmc: fsl_esdhc: support eMMC HS400 mode > > arm: dts: lx2160ardb: support eMMC HS400 mode > > configs: lx2160ardb: enable eMMC HS400 mode support > > > > arch/arm/dts/fsl-lx2160a-rdb.dts | 2 + > > configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + > > configs/lx2160ardb_tfa_defconfig | 1 + > > configs/lx2160ardb_tfa_stmm_defconfig | 1 + > > drivers/mmc/fsl_esdhc.c | 148 > ++++++++++++++++++++++++++- > > drivers/mmc/mmc-uclass.c | 30 ++++++ > > drivers/mmc/mmc.c | 12 ++- > > include/fsl_esdhc.h | 29 +++++- > > include/mmc.h | 26 ++++- > > 9 files changed, 240 insertions(+), 10 deletions(-) > >