Ping on this patch. On 7/5/20 5:47 PM, Parthiban Nallathambi wrote: > MYS-6ULX is single board computer (SBC) comes with eMMC or NAND based > on imx6ULL SoC from NXP and provision for expansion board. This > commit adds support only for SBC with NAND. > > CPU: Freescale i.MX6ULL rev1.1 528 MHz (running at 396 MHz) > CPU: Commercial temperature grade (0C to 95C) at 45C > Reset cause: WDOG > Model: MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND > Board: MYiR MYS-6ULX 6ULL Single Board Computer > DRAM: 256 MiB > NAND: 256 MiB > MMC: FSL_SDHC: 0 > In: serial@2020000 > Out: serial@2020000 > Err: serial@2020000 > Net: FEC0 > > Working: > - Eth0 > - MMC/SD > - NAND > - UART 1 > - USB host > > Signed-off-by: Parthiban Nallathambi <parthi...@linumiz.com> > --- > arch/arm/Kconfig | 1 + > arch/arm/dts/Makefile | 1 + > arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts | 20 ++ > arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi | 238 ++++++++++++++++++++ > arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi | 24 ++ > arch/arm/mach-imx/mx6/Kconfig | 12 + > board/myir/mys_6ulx/Kconfig | 12 + > board/myir/mys_6ulx/MAINTAINERS | 9 + > board/myir/mys_6ulx/Makefile | 4 + > board/myir/mys_6ulx/README | 52 +++++ > board/myir/mys_6ulx/mys_6ulx.c | 146 ++++++++++++ > board/myir/mys_6ulx/spl.c | 206 +++++++++++++++++ > configs/myir_mys_6ulx_defconfig | 66 ++++++ > include/configs/mys_6ulx.h | 80 +++++++ > 14 files changed, 871 insertions(+) > create mode 100644 arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts > create mode 100644 arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi > create mode 100644 arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi > create mode 100644 board/myir/mys_6ulx/Kconfig > create mode 100644 board/myir/mys_6ulx/MAINTAINERS > create mode 100644 board/myir/mys_6ulx/Makefile > create mode 100644 board/myir/mys_6ulx/README > create mode 100644 board/myir/mys_6ulx/mys_6ulx.c > create mode 100644 board/myir/mys_6ulx/spl.c > create mode 100644 configs/myir_mys_6ulx_defconfig > create mode 100644 include/configs/mys_6ulx.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 54d65f8488..24767198e8 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -1905,6 +1905,7 @@ source "board/hisilicon/hikey/Kconfig" > source "board/hisilicon/hikey960/Kconfig" > source "board/hisilicon/poplar/Kconfig" > source "board/isee/igep003x/Kconfig" > +source "board/myir/mys_6ulx/Kconfig" > source "board/silica/pengwyn/Kconfig" > source "board/spear/spear300/Kconfig" > source "board/spear/spear310/Kconfig" > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index 9900b44274..4e06c83234 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -710,6 +710,7 @@ dtb-$(CONFIG_MX6UL) += \ > dtb-$(CONFIG_MX6ULL) += \ > imx6ull-14x14-evk.dtb \ > imx6ull-colibri.dtb \ > + imx6ull-myir-mys-6ulx-eval.dtb \ > imx6ull-phytec-segin-ff-rdk-emmc.dtb \ > imx6ull-dart-6ul.dtb \ > imx6ull-somlabs-visionsom.dtb \ > diff --git a/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts > b/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts > new file mode 100644 > index 0000000000..6bc2d80837 > --- /dev/null > +++ b/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts > @@ -0,0 +1,20 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2020 Linumiz > + * Author: Parthiban Nallathambi <parthi...@linumiz.com> > + */ > + > +/dts-v1/; > +#include "imx6ull.dtsi" > +#include "imx6ull-myir-mys-6ulx.dtsi" > +#include "imx6ull-mys-6ulx-u-boot.dtsi" > + > +/ { > + model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND"; > + compatible = "myir,imx6ull-mys-6ulx-eval", "myir,imx6ull-mys-6ulx", > + "fsl,imx6ull"; > +}; > + > +&gpmi { > + status = "okay"; > +}; > diff --git a/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi > b/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi > new file mode 100644 > index 0000000000..03365a1ca8 > --- /dev/null > +++ b/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi > @@ -0,0 +1,238 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2020 Linumiz > + * Author: Parthiban Nallathambi <parthi...@linumiz.com> > + */ > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/pwm/pwm.h> > + > +/ { > + model = "MYiR MYS-6ULX Single Board Computer"; > + compatible = "myir,imx6ull-mys-6ulx", "fsl,imx6ull"; > + > + chosen { > + stdout-path = &uart1; > + }; > + > + reg_vdd_5v: regulator-vdd-5v { > + compatible = "regulator-fixed"; > + regulator-name = "VDD_5V"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + reg_vdd_3v3: regulator-vdd-3v3 { > + compatible = "regulator-fixed"; > + regulator-name = "VDD_3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + vin-supply = <®_vdd_5v>; > + }; > +}; > + > +&fec1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_enet1>; > + phy-mode = "rmii"; > + phy-handle = <ðphy0>; > + phy-supply = <®_vdd_3v3>; > + status = "okay"; > + > + mdio: mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethphy0: ethernet-phy@0 { > + reg = <0>; > + interrupt-parent = <&gpio5>; > + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&clks IMX6UL_CLK_ENET_REF>; > + clock-names = "rmii-ref"; > + }; > + }; > +}; > + > +&gpmi { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_gpmi_nand>; > + nand-on-flash-bbt; > + status = "disabled"; > +}; > + > +&uart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1>; > + status = "okay"; > +}; > + > +&usbotg1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usb_otg1_id>; > + dr_mode = "otg"; > + status = "okay"; > +}; > + > +&usbotg2 { > + dr_mode = "host"; > + disable-over-current; > + status = "okay"; > +}; > + > +&usdhc1 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc1>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; > + no-1-8-v; > + keep-power-in-suspend; > + wakeup-source; > + vmmc-supply = <®_vdd_3v3>; > + status = "okay"; > +}; > + > +&usdhc2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usdhc2>; > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; > + bus-width = <8>; > + non-removable; > + keep-power-in-suspend; > + vmmc-supply = <®_vdd_3v3>; > +}; > + > +&iomuxc { > + pinctrl_enet1: enet1grp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 > + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 > + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 > + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 > + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 > + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 > + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 > + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 > + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 > + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 > + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 > + >; > + }; > + > + pinctrl_gpmi_nand: gpminandgrp { > + fsl,pins = < > + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 > + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 > + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 > + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 > + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 > + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 > + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 > + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 > + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 > + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 > + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 > + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 > + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 > + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 > + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 > + >; > + }; > + > + pinctrl_uart1: uart1grp { > + fsl,pins = < > + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 > + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 > + >; > + }; > + > + pinctrl_usb_otg1_id: usbotg1idgrp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 > + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 > + >; > + }; > + > + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = < > + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 > + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 > + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 > + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 > + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 > + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 > + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 > + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 > + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 > + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 > + >; > + }; > + > + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { > + fsl,pins = < > + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 > + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 > + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 > + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 > + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 > + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 > + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 > + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 > + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 > + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 > + >; > + }; > + > + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { > + fsl,pins = < > + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 > + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 > + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 > + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 > + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 > + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 > + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 > + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 > + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 > + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 > + >; > + }; > +}; > diff --git a/arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi > b/arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi > new file mode 100644 > index 0000000000..cd15d9ba86 > --- /dev/null > +++ b/arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi > @@ -0,0 +1,24 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2020 Linumiz > + * Author: Parthiban Nallathambi <parthi...@linumiz.com> > + */ > + > +&pinctrl_uart1 { > + u-boot,dm-pre-reloc; > +}; > + > +&gpmi { > + u-boot,dm-spl; > + u-boot,dm-pre-reloc; > +}; > + > +&usdhc1 { > + u-boot,dm-spl; > + u-boot,dm-pre-reloc; > +}; > + > +&usdhc2 { > + u-boot,dm-spl; > + u-boot,dm-pre-reloc; > +}; > diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig > index fa6e1112e6..8dc5d54a92 100644 > --- a/arch/arm/mach-imx/mx6/Kconfig > +++ b/arch/arm/mach-imx/mx6/Kconfig > @@ -460,6 +460,18 @@ config TARGET_MX6ULL_14X14_EVK > select MX6ULL > imply CMD_DM > > +config TARGET_MYS_6ULX > + bool "MYiR MYS-6ULX" > + select MX6ULL > + select DM > + select DM_ETH > + select DM_GPIO > + select DM_I2C > + select DM_MMC > + select DM_SERIAL > + select DM_THERMAL > + select SUPPORT_SPL > + > config TARGET_NITROGEN6X > bool "nitrogen6x" > imply USB_ETHER_ASIX > diff --git a/board/myir/mys_6ulx/Kconfig b/board/myir/mys_6ulx/Kconfig > new file mode 100644 > index 0000000000..cbf72c6eca > --- /dev/null > +++ b/board/myir/mys_6ulx/Kconfig > @@ -0,0 +1,12 @@ > +if TARGET_MYS_6ULX > + > +config SYS_BOARD > + default "mys_6ulx" > + > +config SYS_VENDOR > + default "myir" > + > +config SYS_CONFIG_NAME > + default "mys_6ulx" > + > +endif > diff --git a/board/myir/mys_6ulx/MAINTAINERS b/board/myir/mys_6ulx/MAINTAINERS > new file mode 100644 > index 0000000000..d4ee661182 > --- /dev/null > +++ b/board/myir/mys_6ulx/MAINTAINERS > @@ -0,0 +1,9 @@ > +MYS_6ULX BOARD > +M: Parthiban Nallathambi <parthi...@linumiz.com> > +S: Maintained > +F: arch/arm/dts/imx6ull-myir-mys-6ulx-nand.dts > +F: arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi > +F: arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi > +F: board/myir/mys_6ulx/ > +F: configs/myir_mys_6ulx_defconfig > +F: include/configs/mys_6ulx.h > diff --git a/board/myir/mys_6ulx/Makefile b/board/myir/mys_6ulx/Makefile > new file mode 100644 > index 0000000000..3c63e439ab > --- /dev/null > +++ b/board/myir/mys_6ulx/Makefile > @@ -0,0 +1,4 @@ > +# SPDX-License-Identifier: GPL-2.0+ > + > +obj-y := mys_6ulx.o > +obj-$(CONFIG_SPL_BUILD) += spl.o > diff --git a/board/myir/mys_6ulx/README b/board/myir/mys_6ulx/README > new file mode 100644 > index 0000000000..a0996659c9 > --- /dev/null > +++ b/board/myir/mys_6ulx/README > @@ -0,0 +1,52 @@ > +How to use U-Boot on MYiR MYS-6ULX Single Board Computer > +-------------------------------------------------------- > + > +- Configure and build U-Boot for MYS-6ULX iMX6ULL: > + > + $ make mrproper > + $ make myir_mys_6ulx_defconfig > + $ make > + > + This will generate SPL and u-boot-dtb.img images. > + > +Boot from MMC/SD: > +- The SPL and u-boot-dtb.img images need to be flashed into the micro SD > card: > + > + $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync > + $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync > + > +- Boot mode settings: > + > + Boot switch position: SW1 -> 0 > + SW2 -> 1 > + SW3 -> 0 > + SW4 -> 1 > + > +Boot from NAND: > +- Boot the board using SD/MMC or Serial download and load the SPL into memory > +either from SD/MMC or TFTP. > + > +Default MTD layout is 512k(spl),1m(uboot),1m(uboot-dup),-(ubi) > + > +Flash SPL to NAND from SD/MMC, > + > + $ ext4load mmc 0:2 $loadaddr SPL > + $ nand erase.part spl > + $ nandbcb init $loadaddr 0x0 $filesize > + > +Flash u-boot proper to NAND from SD/MMC, > + > + $ ext4load mmc 0:2 $loadaddr u-boot-dtb.img > + $ nand erase.part uboot > + $ nand write $loadaddr uboot $filesize > + > +- Boot mode settings: > + > + Boot switch position: SW1 -> 1 > + SW2 -> 0 > + SW3 -> 0 > + SW4 -> 1 > + > +- Connect the Serial cable to UART0 and the PC for the console. > + > +- Reset the board using and U-Boot should boot from NAND. > diff --git a/board/myir/mys_6ulx/mys_6ulx.c b/board/myir/mys_6ulx/mys_6ulx.c > new file mode 100644 > index 0000000000..dd6206833b > --- /dev/null > +++ b/board/myir/mys_6ulx/mys_6ulx.c > @@ -0,0 +1,146 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2020 Linumiz > + * Author: Parthiban Nallathambi <parthi...@linumiz.com> > + */ > + > +#include <init.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/crm_regs.h> > +#include <asm/arch/mx6-pins.h> > +#include <asm/arch/sys_proto.h> > +#include <asm/mach-imx/iomux-v3.h> > +#include <asm/mach-imx/mxc_i2c.h> > +#include <fsl_esdhc_imx.h> > +#include <linux/bitops.h> > +#include <miiphy.h> > +#include <netdev.h> > +#include <usb.h> > +#include <usb/ehci-ci.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +int dram_init(void) > +{ > + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); > + > + return 0; > +} > + > +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ > + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ > + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ > + PAD_CTL_HYS) > + > +static iomux_v3_cfg_t const uart1_pads[] = { > + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), > +}; > + > +static iomux_v3_cfg_t const uart5_pads[] = { > + MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), > +}; > + > +static void setup_iomux_uart(void) > +{ > + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); > + imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); > +} > + > +#ifdef CONFIG_FEC_MXC > + > +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) > +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ > + PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \ > + PAD_CTL_SRE_FAST) > +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ > + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \ > + PAD_CTL_ODE) > + > +static iomux_v3_cfg_t const fec1_pads[] = { > + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), > + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), > + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), > +}; > + > +static void setup_iomux_fec(void) > +{ > + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); > +} > + > +static int setup_fec(void) > +{ > + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; > + int ret; > + > + /* > + * Use 50M anatop loopback REF_CLK1 for ENET1, > + * clear gpr1[13], set gpr1[17]. > + */ > + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, > + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); > + > + ret = enable_fec_anatop_clock(0, ENET_50MHZ); > + if (ret) > + return ret; > + > + enable_enet_clk(1); > + > + return 0; > +} > + > +int board_phy_config(struct phy_device *phydev) > +{ > + /* > + * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select > + * 50 MHz RMII clock mode. > + */ > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); > + > + if (phydev->drv->config) > + phydev->drv->config(phydev); > + > + return 0; > +} > +#endif /* CONFIG_FEC_MXC */ > + > +int board_early_init_f(void) > +{ > + setup_iomux_uart(); > +#ifdef CONFIG_FEC_MXC > + setup_iomux_fec(); > +#endif > + > + return 0; > +} > + > +int board_init(void) > +{ > + /* Address of boot parameters */ > + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; > + > +#ifdef CONFIG_FEC_MXC > + setup_fec(); > +#endif > + return 0; > +} > + > +int checkboard(void) > +{ > + u32 cpurev = get_cpu_rev(); > + > + printf("Board: MYiR MYS-6ULX %s Single Board Computer\n", > + get_imx_type((cpurev & 0xFF000) >> 12)); > + > + return 0; > +} > diff --git a/board/myir/mys_6ulx/spl.c b/board/myir/mys_6ulx/spl.c > new file mode 100644 > index 0000000000..72e9012832 > --- /dev/null > +++ b/board/myir/mys_6ulx/spl.c > @@ -0,0 +1,206 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2020 Linumiz > + * Author: Parthiban Nallathambi <parthi...@linumiz.com> > + */ > + > +#include <common.h> > +#include <init.h> > +#include <spl.h> > +#include <asm/arch/clock.h> > +#include <asm/io.h> > +#include <asm/arch/mx6-ddr.h> > +#include <asm/arch/mx6-pins.h> > +#include <asm/arch/crm_regs.h> > +#include <asm/arch/sys_proto.h> > +#include <fsl_esdhc_imx.h> > + > +/* Configuration for Micron MT41K128M16JT-125, 32M x 16 x 8 -> 256MiB */ > + > +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { > + .grp_addds = 0x00000030, > + .grp_ddrmode_ctl = 0x00020000, > + .grp_b0ds = 0x00000030, > + .grp_ctlds = 0x00000030, > + .grp_b1ds = 0x00000030, > + .grp_ddrpke = 0x00000000, > + .grp_ddrmode = 0x00020000, > + .grp_ddr_type = 0x000c0000, > +}; > + > +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { > + .dram_dqm0 = 0x00000030, > + .dram_dqm1 = 0x00000030, > + .dram_ras = 0x00000030, > + .dram_cas = 0x00000030, > + .dram_odt0 = 0x00000030, > + .dram_odt1 = 0x00000030, > + .dram_sdba2 = 0x00000000, > + .dram_sdclk_0 = 0x00000030, > + .dram_sdqs0 = 0x00000030, > + .dram_sdqs1 = 0x00000030, > + .dram_reset = 0x00000030, > +}; > + > +static struct mx6_mmdc_calibration mx6_mmcd_calib = { > + .p0_mpwldectrl0 = 0x00000000, > + .p0_mpdgctrl0 = 0x41480148, > + .p0_mprddlctl = 0x40403E42, > + .p0_mpwrdlctl = 0x40405852, > +}; > + > +struct mx6_ddr_sysinfo ddr_sysinfo = { > + .dsize = 0, /* Bus size = 16bit */ > + .cs_density = 32, > + .ncs = 1, > + .cs1_mirror = 0, > + .rtt_wr = 1, > + .rtt_nom = 1, > + .walat = 1, /* Write additional latency */ > + .ralat = 5, /* Read additional latency */ > + .mif3_mode = 3, /* Command prediction working mode */ > + .bi_on = 1, /* Bank interleaving enabled */ > + .pd_fast_exit = 1, > + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ > + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ > + .ddr_type = DDR_TYPE_DDR3, > + .refsel = 1, /* Refresh cycles at 32KHz */ > + .refr = 7, /* 8 refresh commands per refresh cycle */ > +}; > + > +/* MT41K128M16JT-125 (2Gb density) */ > +static struct mx6_ddr3_cfg mem_ddr = { > + .mem_speed = 1600, > + .density = 2, > + .width = 16, > + .banks = 8, > + .rowaddr = 14, > + .coladdr = 10, > + .pagesz = 2, > + .trcd = 1375, > + .trcmin = 4875, > + .trasmin = 3500, > +}; > + > +static void ccgr_init(void) > +{ > + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; > + > + writel(0xFFFFFFFF, &ccm->CCGR0); > + writel(0xFFFFFFFF, &ccm->CCGR1); > + writel(0xFFFFFFFF, &ccm->CCGR2); > + writel(0xFFFFFFFF, &ccm->CCGR3); > + writel(0xFFFFFFFF, &ccm->CCGR4); > + writel(0xFFFFFFFF, &ccm->CCGR5); > + writel(0xFFFFFFFF, &ccm->CCGR6); > +} > + > +static void spl_dram_init(void) > +{ > + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); > + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); > +} > + > +#ifdef CONFIG_FSL_ESDHC_IMX > + > +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ > + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ > + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ > + PAD_CTL_HYS) > + > +static iomux_v3_cfg_t const usdhc1_pads[] = { > + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), > +}; > + > +#ifndef CONFIG_NAND_MXS > +static iomux_v3_cfg_t const usdhc2_pads[] = { > + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > +}; > +#endif > + > +static struct fsl_esdhc_cfg usdhc_cfg[] = { > + { > + .esdhc_base = USDHC1_BASE_ADDR, > + .max_bus_width = 4, > + }, > +#ifndef CONFIG_NAND_MXS > + { > + .esdhc_base = USDHC2_BASE_ADDR, > + .max_bus_width = 8, > + }, > +#endif > +}; > + > +int board_mmc_getcd(struct mmc *mmc) > +{ > + return 1; > +} > + > +int board_mmc_init(bd_t *bis) > +{ > + int i, ret; > + > + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { > + switch (i) { > + case 0: > + SETUP_IOMUX_PADS(usdhc1_pads); > + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); > + break; > +#ifndef CONFIG_NAND_MXS > + case 1: > + SETUP_IOMUX_PADS(usdhc2_pads); > + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); > + break; > +#endif > + default: > + printf("Warning - USDHC%d controller not supporting\n", > + i + 1); > + return 0; > + } > + > + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); > + if (ret) { > + printf("Warning: failed to initialize mmc dev %d\n", i); > + return ret; > + } > + } > + > + return 0; > +} > + > +#endif /* CONFIG_FSL_ESDHC_IMX */ > + > +void board_init_f(ulong dummy) > +{ > + ccgr_init(); > + > + /* Setup AIPS and disable watchdog */ > + arch_cpu_init(); > + > + /* Setup iomux and fec */ > + board_early_init_f(); > + > + /* Setup GP timer */ > + timer_init(); > + > + /* UART clocks enabled and gd valid - init serial console */ > + preloader_console_init(); > + > + /* DDR initialization */ > + spl_dram_init(); > +} > diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig > new file mode 100644 > index 0000000000..dff27e694f > --- /dev/null > +++ b/configs/myir_mys_6ulx_defconfig > @@ -0,0 +1,66 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_MX6=y > +CONFIG_SYS_TEXT_BASE=0x87800000 > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_ENV_SIZE=0x4000 > +CONFIG_TARGET_MYS_6ULX=y > +CONFIG_SPL_TEXT_BASE=0x908000 > +CONFIG_SPL_MMC_SUPPORT=y > +CONFIG_SPL_SERIAL_SUPPORT=y > +CONFIG_NR_DRAM_BANKS=8 > +CONFIG_SPL=y > +CONFIG_DISTRO_DEFAULTS=y > +CONFIG_FIT=y > +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" > +CONFIG_BOOTDELAY=3 > +# CONFIG_USE_BOOTCOMMAND is not set > +CONFIG_BOARD_EARLY_INIT_F=y > +CONFIG_SPL_DMA=y > +CONFIG_SPL_NAND_SUPPORT=y > +CONFIG_SPL_USB_HOST_SUPPORT=y > +CONFIG_SPL_USB_GADGET=y > +CONFIG_SPL_WATCHDOG_SUPPORT=y > +CONFIG_CMD_DM=y > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_GPT=y > +# CONFIG_RANDOM_UUID is not set > +CONFIG_CMD_I2C=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_MTD=y > +CONFIG_CMD_USB=y > +CONFIG_CMD_CACHE=y > +CONFIG_CMD_MTDPARTS=y > +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" > +CONFIG_MTDPARTS_DEFAULT="gpmi-nand:512k(spl),1m(uboot),1m(uboot-dup),-(ubi)" > +CONFIG_CMD_UBI=y > +# CONFIG_ISO_PARTITION is not set > +CONFIG_OF_CONTROL=y > +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-myir-mys-6ulx-eval" > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > +CONFIG_DM_I2C_GPIO=y > +CONFIG_SYS_I2C_MXC=y > +CONFIG_FSL_USDHC=y > +CONFIG_MTD=y > +CONFIG_DM_MTD=y > +CONFIG_MTD_RAW_NAND=y > +CONFIG_NAND_MXS=y > +CONFIG_NAND_MXS_DT=y > +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y > +CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 > +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x180000 > +CONFIG_PHYLIB=y > +CONFIG_PHY_MICREL=y > +CONFIG_FEC_MXC=y > +CONFIG_MII=y > +CONFIG_PINCTRL=y > +CONFIG_PINCTRL_IMX6=y > +CONFIG_DM_PMIC=y > +# CONFIG_SPL_PMIC_CHILDREN is not set > +CONFIG_DM_REGULATOR=y > +CONFIG_DM_REGULATOR_FIXED=y > +CONFIG_MXC_UART=y > +CONFIG_USB=y > +CONFIG_DM_USB=y > +CONFIG_USB_GADGET=y > +CONFIG_SMBIOS_MANUFACTURER="MYiR" > diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h > new file mode 100644 > index 0000000000..d3bba40271 > --- /dev/null > +++ b/include/configs/mys_6ulx.h > @@ -0,0 +1,80 @@ > +/* SPDX-License-Identifier: GPL-2.0+ > + * > + * Copyright (C) 2020 Linumiz > + * Author: Parthiban Nallathambi <parthi...@linumiz.com> > + */ > + > +#ifndef __MYS_6ULX_H > +#define __MYS_6ULX_H > + > +#include <linux/sizes.h> > +#include "mx6_common.h" > + > +/* SPL options */ > +#include "imx6_spl.h" > + > +#define CONFIG_SYS_FSL_USDHC_NUM 1 > + > +/* Size of malloc() pool */ > +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) > + > +/* Console configs */ > +#define CONFIG_MXC_UART_BASE UART1_BASE > + > +/* MMC Configs */ > +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR > + > +/* Miscellaneous configurable options */ > +#define CONFIG_SYS_MEMTEST_START 0x80000000 > +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + > 0x10000000) > + > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR > +#define CONFIG_SYS_HZ 1000 > + > +/* Physical Memory Map */ > +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR > +#define PHYS_SDRAM_SIZE SZ_256M > + > +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM > +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR > +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE > + > +#define CONFIG_SYS_INIT_SP_OFFSET \ > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > +#define CONFIG_SYS_INIT_SP_ADDR \ > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > + > +/* NAND */ > +#define CONFIG_SYS_MAX_NAND_DEVICE 1 > +#define CONFIG_SYS_NAND_BASE 0x40000000 > + > +/* USB Configs */ > +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET > +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) > +#define CONFIG_MXC_USB_FLAGS 0 > +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 > + > +#define CONFIG_IMX_THERMAL > + > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "console=ttymxc0,115200n8\0" \ > + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ > + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ > + "fdt_addr_r=0x82000000\0" \ > + "fdt_high=0xffffffff\0" \ > + "initrd_high=0xffffffff\0" \ > + "kernel_addr_r=0x81000000\0" \ > + "pxefile_addr_r=0x87100000\0" \ > + "ramdisk_addr_r=0x82100000\0" \ > + "scriptaddr=0x87000000\0" \ > + BOOTENV > + > +#define BOOT_TARGET_DEVICES(func) \ > + func(MMC, mmc, 0) \ > + func(UBIFS, ubifs, 0) \ > + func(PXE, pxe, na) \ > + func(DHCP, dhcp, na) > + > +#include <config_distro_bootcmd.h> > + > +#endif /* __MYS_6ULX_H */ >
-- Thanks, Parthiban N